Lines Matching +full:0 +full:x200
43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
54 reg = <0x20000000 0x10000000>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
67 clock-frequency = <0>;
72 #clock-cells = <0>;
79 reg = <0x00300000 0x8000>;
82 ranges = <0 0x00300000 0x8000>;
101 reg = <0xfffff000 0x200>;
107 reg = <0xffffde00 0x100>;
112 reg = <0xffffe000 0x600>,
113 <0xffffe600 0x200>;
118 reg = <0xffffe800 0x200>;
125 reg = <0xffffea00 0x200>;
130 reg = <0xfffffc00 0x200>;
139 reg = <0xfffffe00 0x10>;
145 reg = <0xfffffe10 0x10>;
151 reg = <0xfffffe30 0xf>;
158 reg = <0xfffffe50 0x4>;
160 #clock-cells = <0>;
166 #size-cells = <0>;
167 reg = <0xf8008000 0x100>;
168 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
176 #size-cells = <0>;
177 reg = <0xf800c000 0x100>;
178 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
185 reg = <0xffffec00 0x200>;
186 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
194 reg = <0xffffee00 0x200>;
195 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
205 ranges = <0xfffff400 0xfffff400 0x800>;
209 pinctrl_dbgu: dbgu-0 {
217 pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
229 pinctrl_ebi_data_8_15: ebi-data-msb-0 {
241 pinctrl_ebi_addr_nand: ebi-addr-0 {
249 pinctrl_usart0: usart0-0 {
251 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
255 pinctrl_usart0_rts: usart0_rts-0 {
260 pinctrl_usart0_cts: usart0_cts-0 {
265 pinctrl_usart0_sck: usart0_sck-0 {
272 pinctrl_usart1: usart1-0 {
278 pinctrl_usart1_rts: usart1_rts-0 {
283 pinctrl_usart1_cts: usart1_cts-0 {
288 pinctrl_usart1_sck: usart1_sck-0 {
295 pinctrl_usart2: usart2-0 {
301 pinctrl_usart2_rts: usart2_rts-0 {
303 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
306 pinctrl_usart2_cts: usart2_cts-0 {
311 pinctrl_usart2_sck: usart2_sck-0 {
318 pinctrl_uart0: uart0-0 {
326 pinctrl_uart1: uart1-0 {
334 pinctrl_nand_oe_we: nand-oe-we-0 {
336 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE
340 pinctrl_nand_rb: nand-rb-0 {
345 pinctrl_nand_cs: nand-cs-0 {
352 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
359 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
368 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
375 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
384 pinctrl_ssc0_tx: ssc0_tx-0 {
391 pinctrl_ssc0_rx: ssc0_rx-0 {
400 pinctrl_spi0: spi0-0 {
409 pinctrl_spi1: spi1-0 {
418 pinctrl_i2c0: i2c0-0 {
426 pinctrl_i2c1: i2c1-0 {
428 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */
434 pinctrl_i2c2: i2c2-0 {
442 pinctrl_i2c_gpio0: i2c_gpio0-0 {
450 pinctrl_i2c_gpio1: i2c_gpio1-0 {
452 <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */
458 pinctrl_i2c_gpio2: i2c_gpio2-0 {
466 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
479 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
492 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
501 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
512 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
516 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
520 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
524 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
528 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
532 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
536 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
540 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
544 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
550 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
554 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
558 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
562 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
566 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
570 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
574 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
578 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
582 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
589 reg = <0xfffff400 0x200>;
600 reg = <0xfffff600 0x200>;
612 reg = <0xfffff800 0x200>;
623 reg = <0xfffffa00 0x200>;
636 reg = <0xf0010000 0x4000>;
642 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
650 reg = <0xf0008000 0x600>;
651 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
652 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
657 #size-cells = <0>;
663 reg = <0xf000c000 0x600>;
664 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
665 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
670 #size-cells = <0>;
676 reg = <0xfffff200 0x200>;
679 pinctrl-0 = <&pinctrl_dbgu>;
690 reg = <0xf801c000 0x200>;
693 pinctrl-0 = <&pinctrl_usart0>;
704 reg = <0xf8020000 0x200>;
707 pinctrl-0 = <&pinctrl_usart1>;
718 reg = <0xf8024000 0x200>;
721 pinctrl-0 = <&pinctrl_usart2>;
732 reg = <0xf8010000 0x100>;
738 #size-cells = <0>;
740 pinctrl-0 = <&pinctrl_i2c0>;
747 reg = <0xf8014000 0x100>;
753 #size-cells = <0>;
755 pinctrl-0 = <&pinctrl_i2c1>;
762 reg = <0xf8018000 0x100>;
768 #size-cells = <0>;
770 pinctrl-0 = <&pinctrl_i2c2>;
777 reg = <0xf8040000 0x200>;
780 pinctrl-0 = <&pinctrl_uart0>;
788 reg = <0xf8044000 0x200>;
791 pinctrl-0 = <&pinctrl_uart1>;
799 #size-cells = <0>;
801 reg = <0xf804c000 0x100>;
802 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
807 atmel,adc-channels-used = <0xffff>;
817 trigger-value = <0x1>;
823 trigger-value = <0x2>;
829 trigger-value = <0x3>;
835 trigger-value = <0x6>;
841 #size-cells = <0>;
843 reg = <0xf0000000 0x100>;
849 pinctrl-0 = <&pinctrl_spi0>;
857 #size-cells = <0>;
859 reg = <0xf0004000 0x100>;
865 pinctrl-0 = <&pinctrl_spi1>;
873 reg = <0x00500000 0x80000
874 0xf803c000 0x400>;
875 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
883 reg = <0xfffffe40 0x10>;
894 reg = <0xfffffeb0 0x40>;
902 reg = <0xf8034000 0x300>;
912 reg = <0x00600000 0x100000>;
921 reg = <0x00700000 0x100000>;
934 reg = <0x10000000 0x60000000>;
935 ranges = <0x0 0x0 0x10000000 0x10000000
936 0x1 0x0 0x20000000 0x10000000
937 0x2 0x0 0x30000000 0x10000000
938 0x3 0x0 0x40000000 0x10000000
939 0x4 0x0 0x50000000 0x10000000
940 0x5 0x0 0x60000000 0x10000000>;
955 i2c-gpio-0 {
964 #size-cells = <0>;
966 pinctrl-0 = <&pinctrl_i2c_gpio0>;
972 gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
979 #size-cells = <0>;
981 pinctrl-0 = <&pinctrl_i2c_gpio1>;
994 #size-cells = <0>;
996 pinctrl-0 = <&pinctrl_i2c_gpio2>;