Lines Matching +full:0 +full:x200
42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0>;
53 reg = <0x20000000 0x04000000>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 reg = <0x00300000 0x10000>;
81 ranges = <0 0x00300000 0x10000>;
92 reg = <0x00500000 0x1000>;
95 pinctrl-0 = <&pinctrl_fb>;
107 reg = <0x10000000 0x80000000>;
108 ranges = <0x0 0x0 0x10000000 0x10000000
109 0x1 0x0 0x20000000 0x10000000
110 0x2 0x0 0x30000000 0x10000000
111 0x3 0x0 0x40000000 0x10000000
112 0x4 0x0 0x50000000 0x10000000
113 0x5 0x0 0x60000000 0x10000000>;
135 #size-cells = <0>;
136 reg = <0xfffa0000 0x100>;
137 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
138 <17 IRQ_TYPE_LEVEL_HIGH 0>,
139 <18 IRQ_TYPE_LEVEL_HIGH 0>;
146 reg = <0xfffa4000 0x600>;
147 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
149 #size-cells = <0>;
158 reg = <0xfffa8000 0x100>;
161 #size-cells = <0>;
168 reg = <0xfffac000 0x100>;
171 #size-cells = <0>;
177 reg = <0xfffb0000 0x200>;
182 pinctrl-0 = <&pinctrl_usart0>;
190 reg = <0xfffb4000 0x200>;
195 pinctrl-0 = <&pinctrl_usart1>;
203 reg = <0xfffb8000 0x200>;
208 pinctrl-0 = <&pinctrl_usart2>;
216 reg = <0xfffbc000 0x200>;
221 pinctrl-0 = <&pinctrl_usart3>;
229 reg = <0xfffc0000 0x4000>;
232 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
238 reg = <0xfffc4000 0x4000>;
241 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
247 reg = <0xfffc8000 0x300>;
257 #size-cells = <0>;
259 reg = <0xfffcc000 0x200>;
262 pinctrl-0 = <&pinctrl_spi0>;
270 #size-cells = <0>;
272 reg = <0xfffd0000 0x100>;
273 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
277 atmel,adc-channels-used = <0x3f>;
285 trigger-name = "timer-counter-0";
286 trigger-value = <0x1>;
290 trigger-value = <0x3>;
295 trigger-value = <0x5>;
300 trigger-value = <0x13>;
307 reg = <0x00600000 0x100000>,
308 <0xfffd4000 0x4000>;
317 reg = <0xffffe600 0x200>;
318 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
326 reg = <0xffffea00 0x200>;
331 reg = <0xffffec00 0x200>;
336 reg = <0xffffee00 0x200>;
343 reg = <0xfffff000 0x200>;
349 reg = <0xfffff200 0x200>;
352 pinctrl-0 = <&pinctrl_dbgu>;
362 ranges = <0xfffff400 0xfffff400 0x800>;
366 <0xffffffff 0xe05c6738>, /* pioA */
367 <0xffffffff 0x0000c780>, /* pioB */
368 <0xffffffff 0xe3ffff0e>, /* pioC */
369 <0x003fffff 0x0001ff3c>; /* pioD */
373 pinctrl_adc0_ts: adc0_ts-0 {
381 pinctrl_adc0_ad0: adc0_ad0-0 {
385 pinctrl_adc0_ad1: adc0_ad1-0 {
389 pinctrl_adc0_ad2: adc0_ad2-0 {
393 pinctrl_adc0_ad3: adc0_ad3-0 {
397 pinctrl_adc0_ad4: adc0_ad4-0 {
401 pinctrl_adc0_ad5: adc0_ad5-0 {
405 pinctrl_adc0_adtrg: adc0_adtrg-0 {
411 pinctrl_dbgu: dbgu-0 {
419 pinctrl_ebi_addr_nand: ebi-addr-0 {
427 pinctrl_fb: fb-0 {
454 pinctrl_i2c_gpio0: i2c_gpio0-0 {
462 pinctrl_i2c_gpio1: i2c_gpio1-0 {
470 pinctrl_mmc0_clk: mmc0_clk-0 {
475 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
477 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
481 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
490 pinctrl_nand_rb: nand-rb-0 {
495 pinctrl_nand_cs: nand-cs-0 {
500 pinctrl_nand_oe_we: nand-oe-we-0 {
508 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
520 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
532 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
544 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
554 pinctrl_spi0: spi0-0 {
563 pinctrl_ssc0_tx: ssc0_tx-0 {
566 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
570 pinctrl_ssc0_rx: ssc0_rx-0 {
579 pinctrl_ssc1_tx: ssc1_tx-0 {
586 pinctrl_ssc1_rx: ssc1_rx-0 {
595 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
599 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
603 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
607 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
611 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
615 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
619 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
623 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
627 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
633 pinctrl_usart0: usart0-0 {
639 pinctrl_usart0_rts: usart0_rts-0 {
644 pinctrl_usart0_cts: usart0_cts-0 {
649 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
655 pinctrl_usart0_dcd: usart0_dcd-0 {
660 pinctrl_usart0_ri: usart0_ri-0 {
665 pinctrl_usart0_sck: usart0_sck-0 {
672 pinctrl_usart1: usart1-0 {
678 pinctrl_usart1_rts: usart1_rts-0 {
683 pinctrl_usart1_cts: usart1_cts-0 {
688 pinctrl_usart1_sck: usart1_sck-0 {
695 pinctrl_usart2: usart2-0 {
701 pinctrl_usart2_rts: usart2_rts-0 {
706 pinctrl_usart2_cts: usart2_cts-0 {
711 pinctrl_usart2_sck: usart2_sck-0 {
718 pinctrl_usart3: usart3-0 {
720 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
724 pinctrl_usart3_rts: usart3_rts-0 {
729 pinctrl_usart3_cts: usart3_cts-0 {
734 pinctrl_usart3_sck: usart3_sck-0 {
742 reg = <0xfffff400 0x200>;
753 reg = <0xfffff600 0x200>;
764 reg = <0xfffff800 0x200>;
775 reg = <0xfffffa00 0x200>;
787 reg = <0xfffffc00 0x100>;
796 reg = <0xfffffd00 0x10>;
802 reg = <0xfffffd10 0x10>;
808 reg = <0xfffffd30 0xf>;
815 reg = <0xfffffd40 0x10>;
823 reg = <0xfffffd50 0x4>;
825 #clock-cells = <0>;
830 reg = <0xfffffd20 0x10>;
838 reg = <0xfffffd60 0x10>;
844 reg = <0xfffffe00 0x40>;
853 i2c-gpio-0 {
861 #size-cells = <0>;
863 pinctrl-0 = <&pinctrl_i2c_gpio0>;
875 #size-cells = <0>;
877 pinctrl-0 = <&pinctrl_i2c_gpio1>;