Lines Matching +full:0 +full:xfffffe00
41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0>;
52 reg = <0x20000000 0x10000000>;
58 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #clock-cells = <0>;
65 clock-frequency = <0>;
71 reg = <0x00300000 0x8000>;
74 ranges = <0 0x00300000 0x8000>;
93 reg = <0xfffff000 0x200>;
99 reg = <0xffffde00 0x100>;
104 reg = <0xffffe000 0x600>,
105 <0xffffe600 0x200>;
110 reg = <0xffffe800 0x200>;
117 reg = <0xffffea00 0x200>;
122 reg = <0xfffffc00 0x200>;
131 reg = <0xfffffe00 0x10>;
137 reg = <0xfffffe30 0xf>;
144 reg = <0xfffffe10 0x10>;
150 reg = <0xfffffe50 0x4>;
154 #clock-cells = <0>;
160 #clock-cells = <0>;
167 #clock-cells = <0>;
174 reg = <0xf0008000 0x600>;
175 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
176 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
181 #size-cells = <0>;
188 #size-cells = <0>;
189 reg = <0xf8008000 0x100>;
190 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
198 #size-cells = <0>;
199 reg = <0xf800c000 0x100>;
200 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
207 reg = <0xf8038000 0x2000>;
208 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
216 #size-cells = <0>;
218 port@0 {
220 #size-cells = <0>;
221 reg = <0>;
228 pinctrl-0 = <&pinctrl_lcd_pwm>;
235 reg = <0xffffec00 0x200>;
236 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
246 ranges = <0xfffff400 0xfffff400 0x800>;
250 0xffffffff 0xffe07983 0x00000000 /* pioA */
251 0x00040000 0x00047e0f 0x00000000 /* pioB */
252 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
253 0x003fffff 0x003f8000 0x00000000 /* pioD */
258 pinctrl_dbgu: dbgu-0 {
266 pinctrl_lcd_base: lcd-base-0 {
275 pinctrl_lcd_pwm: lcd-pwm-0 {
281 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
309 pinctrl_usart0: usart0-0 {
312 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
315 pinctrl_usart0_rts: usart0_rts-0 {
320 pinctrl_usart0_cts: usart0_cts-0 {
327 pinctrl_usart1: usart1-0 {
335 pinctrl_usart2: usart2-0 {
341 pinctrl_usart2_rts: usart2_rts-0 {
343 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
346 pinctrl_usart2_cts: usart2_cts-0 {
353 pinctrl_usart3: usart3-0 {
359 pinctrl_usart3_rts: usart3_rts-0 {
364 pinctrl_usart3_cts: usart3_cts-0 {
371 pinctrl_uart0: uart0-0 {
379 pinctrl_uart1: uart1-0 {
387 pinctrl_nand_rb: nand-rb-0 {
392 pinctrl_nand_cs: nand-cs-0 {
399 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
406 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
413 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
423 pinctrl_ssc0_tx: ssc0_tx-0 {
430 pinctrl_ssc0_rx: ssc0_rx-0 {
439 pinctrl_spi0: spi0-0 {
448 pinctrl_spi1: spi1-0 {
457 pinctrl_i2c0: i2c0-0 {
465 pinctrl_i2c1: i2c1-0 {
467 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
473 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
477 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
481 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
485 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
489 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
493 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
497 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
501 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
505 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
511 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
515 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
519 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
523 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
527 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
531 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
535 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
539 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
543 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
550 reg = <0xfffff400 0x200>;
561 reg = <0xfffff600 0x200>;
572 reg = <0xfffff800 0x200>;
583 reg = <0xfffffa00 0x200>;
595 reg = <0xfffff200 0x200>;
598 pinctrl-0 = <&pinctrl_dbgu>;
606 reg = <0xf0010000 0x4000>;
608 dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>,
609 <&dma 0 AT91_DMA_CFG_PER_ID(22)>;
612 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
620 reg = <0xf801c000 0x4000>;
623 pinctrl-0 = <&pinctrl_usart0>;
631 reg = <0xf8020000 0x4000>;
634 pinctrl-0 = <&pinctrl_usart1>;
642 reg = <0xf8024000 0x4000>;
645 pinctrl-0 = <&pinctrl_usart2>;
653 reg = <0xf8028000 0x4000>;
656 pinctrl-0 = <&pinctrl_usart3>;
664 reg = <0xf8010000 0x100>;
670 #size-cells = <0>;
672 pinctrl-0 = <&pinctrl_i2c0>;
679 reg = <0xf8014000 0x100>;
685 #size-cells = <0>;
687 pinctrl-0 = <&pinctrl_i2c1>;
694 #size-cells = <0>;
696 reg = <0xf0000000 0x100>;
702 pinctrl-0 = <&pinctrl_spi0>;
710 #size-cells = <0>;
712 reg = <0xf0004000 0x100>;
718 pinctrl-0 = <&pinctrl_spi1>;
726 reg = <0xfffffe40 0x10>;
737 reg = <0xfffffeb0 0x40>;
745 reg = <0xf8034000 0x300>;
754 reg = <0xf803c000 0x4000>;
764 reg = <0x00500000 0x00100000>;
777 reg = <0x10000000 0x60000000>;
778 ranges = <0x0 0x0 0x10000000 0x10000000
779 0x1 0x0 0x20000000 0x10000000
780 0x2 0x0 0x30000000 0x10000000
781 0x3 0x0 0x40000000 0x10000000
782 0x4 0x0 0x50000000 0x10000000
783 0x5 0x0 0x60000000 0x10000000>;
798 i2c-gpio-0 {
807 #size-cells = <0>;