Lines Matching +full:0 +full:x200
45 #size-cells = <0>;
47 cpu@0 {
50 reg = <0>;
56 reg = <0x70000000 0x10000000>;
62 #clock-cells = <0>;
63 clock-frequency = <0>;
68 #clock-cells = <0>;
69 clock-frequency = <0>;
74 #clock-cells = <0>;
81 reg = <0x00300000 0x10000>;
84 ranges = <0 0x00300000 0x10000>;
103 reg = <0xfffff000 0x200>;
109 reg = <0xffffe400 0x200>;
116 reg = <0xffffe600 0x200>;
123 reg = <0xffffe800 0x200>;
128 reg = <0xffffea00 0x200>;
133 reg = <0xfffffc00 0x100>;
142 reg = <0xfffffd00 0x10>;
148 reg = <0xfffffd30 0xf>;
156 reg = <0xfffffd10 0x10>;
163 #size-cells = <0>;
164 reg = <0xfff7c000 0x100>;
165 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
173 #size-cells = <0>;
174 reg = <0xfffd4000 0x100>;
175 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
182 reg = <0xffffec00 0x200>;
183 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
193 ranges = <0xfffff200 0xfffff200 0xa00>;
197 0xffffffff 0xffc003ff /* pioA */
198 0xffffffff 0x800f8f00 /* pioB */
199 0xffffffff 0x00000e00 /* pioC */
200 0xffffffff 0xff0c1381 /* pioD */
201 0xffffffff 0x81ffff81 /* pioE */
206 pinctrl_ac97: ac97-0 {
246 pinctrl_dbgu: dbgu-0 {
254 pinctrl_i2c0: i2c0-0 {
262 pinctrl_i2c1: i2c1-0 {
270 pinctrl_isi_data_0_7: isi-0-data-0-7 {
285 pinctrl_isi_data_8_9: isi-0-data-8-9 {
291 pinctrl_isi_data_10_11: isi-0-data-10-11 {
299 pinctrl_usart0: usart0-0 {
305 pinctrl_usart0_rts: usart0_rts-0 {
310 pinctrl_usart0_cts: usart0_cts-0 {
317 pinctrl_usart1: usart1-0 {
323 pinctrl_usart1_rts: usart1_rts-0 {
328 pinctrl_usart1_cts: usart1_cts-0 {
335 pinctrl_usart2: usart2-0 {
341 pinctrl_usart2_rts: usart2_rts-0 {
346 pinctrl_usart2_cts: usart2_cts-0 {
353 pinctrl_usart3: usart3-0 {
359 pinctrl_usart3_rts: usart3_rts-0 {
364 pinctrl_usart3_cts: usart3_cts-0 {
371 pinctrl_nand_rb: nand-rb-0 {
376 pinctrl_nand_cs: nand-cs-0 {
383 pinctrl_macb_rmii: macb_rmii-0 {
397 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
411 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
413 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
418 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
425 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
435 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
442 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
449 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
459 pinctrl_ssc0_tx: ssc0_tx-0 {
461 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
466 pinctrl_ssc0_rx: ssc0_rx-0 {
475 pinctrl_ssc1_tx: ssc1_tx-0 {
482 pinctrl_ssc1_rx: ssc1_rx-0 {
491 pinctrl_spi0: spi0-0 {
493 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
500 pinctrl_spi1: spi1-0 {
509 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
513 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
517 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
521 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
525 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
529 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
533 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
537 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
541 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
547 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
548 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
551 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
555 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
559 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
563 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
567 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
571 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
575 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
579 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
585 pinctrl_fb: fb-0 {
587 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
622 reg = <0xfffff200 0x200>;
633 reg = <0xfffff400 0x200>;
644 reg = <0xfffff600 0x200>;
655 reg = <0xfffff800 0x200>;
666 reg = <0xfffffa00 0x200>;
678 reg = <0xffffee00 0x200>;
681 pinctrl-0 = <&pinctrl_dbgu>;
689 reg = <0xfff8c000 0x200>;
694 pinctrl-0 = <&pinctrl_usart0>;
702 reg = <0xfff90000 0x200>;
707 pinctrl-0 = <&pinctrl_usart1>;
715 reg = <0xfff94000 0x200>;
720 pinctrl-0 = <&pinctrl_usart2>;
728 reg = <0xfff98000 0x200>;
733 pinctrl-0 = <&pinctrl_usart3>;
741 reg = <0xfffbc000 0x100>;
744 pinctrl-0 = <&pinctrl_macb_rmii>;
752 reg = <0xfffcc000 0x100>;
753 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
759 reg = <0xfff84000 0x100>;
762 pinctrl-0 = <&pinctrl_i2c0>;
764 #size-cells = <0>;
771 reg = <0xfff88000 0x100>;
774 pinctrl-0 = <&pinctrl_i2c1>;
776 #size-cells = <0>;
783 reg = <0xfff9c000 0x4000>;
786 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
794 reg = <0xfffa0000 0x4000>;
797 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
805 reg = <0xfffac000 0x4000>;
808 pinctrl-0 = <&pinctrl_ac97>;
816 #size-cells = <0>;
818 reg = <0xfffb0000 0x100>;
819 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
822 atmel,adc-channels-used = <0xff>;
831 trigger-value = <0x1>;
836 trigger-value = <0x2>;
842 trigger-value = <0x3>;
848 trigger-value = <0x6>;
854 reg = <0xfffb4000 0x4000>;
861 #size-cells = <0>;
867 reg = <0xfffb8000 0x300>;
876 reg = <0xfff80000 0x600>;
877 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
878 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
881 #size-cells = <0>;
889 reg = <0xfffd0000 0x600>;
890 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
894 #size-cells = <0>;
902 reg = <0xfffffd40 0x10>;
913 #size-cells = <0>;
915 reg = <0xfffa4000 0x200>;
918 pinctrl-0 = <&pinctrl_spi0>;
926 #size-cells = <0>;
928 reg = <0xfffa8000 0x200>;
931 pinctrl-0 = <&pinctrl_spi1>;
939 reg = <0x00600000 0x80000
940 0xfff78000 0x400>;
941 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
949 reg = <0xfffffd50 0x4>;
951 #clock-cells = <0>;
956 reg = <0xfffffd20 0x10>;
964 reg = <0xfffffdb0 0x30>;
972 reg = <0xfffffd60 0x10>;
979 reg = <0x00500000 0x1000>;
982 pinctrl-0 = <&pinctrl_fb>;
990 reg = <0x00700000 0x100000>;
999 reg = <0x00800000 0x100000>;
1012 reg = <0x10000000 0x80000000>;
1013 ranges = <0x0 0x0 0x10000000 0x10000000
1014 0x1 0x0 0x20000000 0x10000000
1015 0x2 0x0 0x30000000 0x10000000
1016 0x3 0x0 0x40000000 0x10000000
1017 0x4 0x0 0x50000000 0x10000000
1018 0x5 0x0 0x60000000 0x10000000>;
1032 i2c-gpio-0 {
1041 #size-cells = <0>;