Lines Matching +full:0 +full:x200
39 #size-cells = <0>;
41 cpu@0 {
44 reg = <0>;
50 reg = <0x20000000 0x08000000>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #clock-cells = <0>;
63 clock-frequency = <0>;
69 reg = <0x00300000 0x14000>;
72 ranges = <0 0x00300000 0x14000>;
77 reg = <0x00500000 0x4000>;
80 ranges = <0 0x00500000 0x4000>;
99 reg = <0xfffff000 0x200>;
105 reg = <0xfffffc00 0x100>;
114 reg = <0xffffe200 0x200>;
119 reg = <0xffffe400 0x200>;
124 reg = <0xffffe800 0x200>;
129 reg = <0xffffea00 0x200>;
134 reg = <0xffffec00 0x200>;
139 reg = <0xfffffd30 0xf>;
147 #size-cells = <0>;
148 reg = <0xfff7c000 0x100>;
149 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
156 reg = <0xfffffd00 0x10>;
162 reg = <0xfffffd10 0x10>;
170 ranges = <0xfffff200 0xfffff200 0xa00>;
174 0xfffffffb 0xffffe07f /* pioA */
175 0x0007ffff 0x39072fff /* pioB */
176 0xffffffff 0x3ffffff8 /* pioC */
177 0xfffffbff 0xffffffff /* pioD */
178 0xffe00fff 0xfbfcff00 /* pioE */
183 pinctrl_dbgu: dbgu-0 {
191 pinctrl_usart0: usart0-0 {
197 pinctrl_usart0_rts: usart0_rts-0 {
202 pinctrl_usart0_cts: usart0_cts-0 {
209 pinctrl_usart1: usart1-0 {
211 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
215 pinctrl_usart1_rts: usart1_rts-0 {
220 pinctrl_usart1_cts: usart1_cts-0 {
227 pinctrl_usart2: usart2-0 {
233 pinctrl_usart2_rts: usart2_rts-0 {
238 pinctrl_usart2_cts: usart2_cts-0 {
245 pinctrl_nand_rb: nand-rb-0 {
250 pinctrl_nand_cs: nand-cs-0 {
257 pinctrl_macb_rmii: macb_rmii-0 {
271 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
285 pinctrl_mmc0_clk: mmc0_clk-0 {
290 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
293 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */
296 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
303 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
309 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
318 pinctrl_mmc1_clk: mmc1_clk-0 {
323 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
329 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
336 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
342 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
351 pinctrl_ssc0_tx: ssc0_tx-0 {
353 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */
358 pinctrl_ssc0_rx: ssc0_rx-0 {
367 pinctrl_ssc1_tx: ssc1_tx-0 {
374 pinctrl_ssc1_rx: ssc1_rx-0 {
383 pinctrl_spi0: spi0-0 {
385 <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */
392 pinctrl_spi1: spi1-0 {
401 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
405 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
409 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
413 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
417 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
421 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
425 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
429 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
433 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
439 pinctrl_fb: fb-0 {
475 pinctrl_ac97: ac97-0 {
477 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A AC97FS pin */
486 reg = <0xfffff200 0x200>;
497 reg = <0xfffff400 0x200>;
508 reg = <0xfffff600 0x200>;
519 reg = <0xfffff800 0x200>;
530 reg = <0xfffffa00 0x200>;
542 reg = <0xffffee00 0x200>;
545 pinctrl-0 = <&pinctrl_dbgu>;
553 reg = <0xfff8c000 0x200>;
558 pinctrl-0 = <&pinctrl_usart0>;
566 reg = <0xfff90000 0x200>;
571 pinctrl-0 = <&pinctrl_usart1>;
579 reg = <0xfff94000 0x200>;
584 pinctrl-0 = <&pinctrl_usart2>;
592 reg = <0xfff98000 0x4000>;
595 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
603 reg = <0xfff9c000 0x4000>;
606 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
614 reg = <0xfffa0000 0x4000>;
617 pinctrl-0 = <&pinctrl_ac97>;
625 reg = <0xfffbc000 0x100>;
628 pinctrl-0 = <&pinctrl_macb_rmii>;
636 reg = <0xfff78000 0x4000>;
645 reg = <0xfff88000 0x100>;
648 #size-cells = <0>;
655 reg = <0xfff80000 0x600>;
656 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
658 #size-cells = <0>;
666 reg = <0xfff84000 0x600>;
667 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
669 #size-cells = <0>;
677 reg = <0xfffffd40 0x10>;
688 #size-cells = <0>;
690 reg = <0xfffa4000 0x200>;
693 pinctrl-0 = <&pinctrl_spi0>;
701 #size-cells = <0>;
703 reg = <0xfffa8000 0x200>;
706 pinctrl-0 = <&pinctrl_spi1>;
714 reg = <0xfffb8000 0x300>;
724 reg = <0xfffac000 0x300>;
727 pinctrl-0 = <&pinctrl_can_rx_tx>;
734 reg = <0xfffffd20 0x10>;
742 reg = <0xfffffd50 0x10>;
750 reg = <0xfffffd60 0x50>;
757 reg = <0x00700000 0x1000>;
760 pinctrl-0 = <&pinctrl_fb>;
768 reg = <0x00a00000 0x100000>;
781 reg = <0x10000000 0x80000000>;
782 ranges = <0x0 0x0 0x10000000 0x10000000
783 0x1 0x0 0x20000000 0x10000000
784 0x2 0x0 0x30000000 0x10000000
785 0x3 0x0 0x40000000 0x10000000
786 0x4 0x0 0x50000000 0x10000000
787 0x5 0x0 0x60000000 0x10000000>;
806 reg = <0x80000000 0x20000000>;
807 ranges = <0x0 0x0 0x80000000 0x10000000
808 0x1 0x0 0x90000000 0x10000000>;
822 i2c-gpio-0 {
831 #size-cells = <0>;