Lines Matching +full:0 +full:x200
40 #size-cells = <0>;
42 cpu@0 {
45 reg = <0>;
51 reg = <0x20000000 0x04000000>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
63 #clock-cells = <0>;
64 clock-frequency = <0>;
69 #clock-cells = <0>;
76 reg = <0x002ff000 0x2000>;
79 ranges = <0 0x002ff000 0x2000>;
98 reg = <0xfffff000 0x200>;
104 reg = <0xffffea00 0x200>;
109 reg = <0xffffec00 0x200>;
114 reg = <0xffffee00 0x200>;
119 reg = <0xfffffc00 0x100>;
128 reg = <0xfffffd00 0x10>;
134 reg = <0xfffffd10 0x10>;
140 reg = <0xfffffd30 0xf>;
148 #size-cells = <0>;
149 reg = <0xfffa0000 0x100>;
150 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
151 18 IRQ_TYPE_LEVEL_HIGH 0
152 19 IRQ_TYPE_LEVEL_HIGH 0>;
160 #size-cells = <0>;
161 reg = <0xfffdc000 0x100>;
162 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
163 27 IRQ_TYPE_LEVEL_HIGH 0
164 28 IRQ_TYPE_LEVEL_HIGH 0>;
173 ranges = <0xfffff400 0xfffff400 0x600>;
177 0xffffffff 0xffc00c3b /* pioA */
178 0xffffffff 0x7fff3ccf /* pioB */
179 0xffffffff 0x007fffff /* pioC */
184 pinctrl_dbgu: dbgu-0 {
192 pinctrl_usart0: usart0-0 {
198 pinctrl_usart0_rts: usart0_rts-0 {
203 pinctrl_usart0_cts: usart0_cts-0 {
208 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
214 pinctrl_usart0_dcd: usart0_dcd-0 {
219 pinctrl_usart0_ri: usart0_ri-0 {
226 pinctrl_usart1: usart1-0 {
232 pinctrl_usart1_rts: usart1_rts-0 {
237 pinctrl_usart1_cts: usart1_cts-0 {
244 pinctrl_usart2: usart2-0 {
250 pinctrl_usart2_rts: usart2_rts-0 {
255 pinctrl_usart2_cts: usart2_cts-0 {
262 pinctrl_usart3: usart3-0 {
268 pinctrl_usart3_rts: usart3_rts-0 {
273 pinctrl_usart3_cts: usart3_cts-0 {
280 pinctrl_uart0: uart0-0 {
288 pinctrl_uart1: uart1-0 {
296 pinctrl_nand_rb: nand-rb-0 {
301 pinctrl_nand_cs: nand-cs-0 {
308 pinctrl_macb_rmii: macb_rmii-0 {
322 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
348 pinctrl_mmc0_clk: mmc0_clk-0 {
353 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
359 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
366 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
369 AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */
372 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
381 pinctrl_ssc0_tx: ssc0_tx-0 {
388 pinctrl_ssc0_rx: ssc0_rx-0 {
397 pinctrl_spi0: spi0-0 {
399 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
406 pinctrl_spi1: spi1-0 {
408 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */
415 pinctrl_i2c_gpio0: i2c_gpio0-0 {
423 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
427 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
431 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
435 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
439 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
443 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
447 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
451 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
455 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
461 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
465 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
469 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
473 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
474 atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
477 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
481 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
485 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
489 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
493 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
500 reg = <0xfffff400 0x200>;
511 reg = <0xfffff600 0x200>;
522 reg = <0xfffff800 0x200>;
534 reg = <0xfffff200 0x200>;
537 pinctrl-0 = <&pinctrl_dbgu>;
545 reg = <0xfffb0000 0x200>;
550 pinctrl-0 = <&pinctrl_usart0>;
558 reg = <0xfffb4000 0x200>;
563 pinctrl-0 = <&pinctrl_usart1>;
571 reg = <0xfffb8000 0x200>;
576 pinctrl-0 = <&pinctrl_usart2>;
584 reg = <0xfffd0000 0x200>;
589 pinctrl-0 = <&pinctrl_usart3>;
597 reg = <0xfffd4000 0x200>;
602 pinctrl-0 = <&pinctrl_uart0>;
610 reg = <0xfffd8000 0x200>;
615 pinctrl-0 = <&pinctrl_uart1>;
623 reg = <0xfffc4000 0x100>;
626 pinctrl-0 = <&pinctrl_macb_rmii>;
634 reg = <0xfffa4000 0x4000>;
643 reg = <0xfffac000 0x100>;
646 #size-cells = <0>;
653 reg = <0xfffa8000 0x600>;
654 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
656 #size-cells = <0>;
664 reg = <0xfffbc000 0x4000>;
667 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
675 #size-cells = <0>;
677 reg = <0xfffc8000 0x200>;
680 pinctrl-0 = <&pinctrl_spi0>;
688 #size-cells = <0>;
690 reg = <0xfffcc000 0x200>;
693 pinctrl-0 = <&pinctrl_spi1>;
701 #size-cells = <0>;
703 reg = <0xfffe0000 0x100>;
704 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
708 atmel,adc-channels-used = <0xf>;
716 trigger-name = "timer-counter-0";
717 trigger-value = <0x1>;
721 trigger-value = <0x3>;
726 trigger-value = <0x5>;
731 trigger-value = <0xd>;
738 reg = <0xfffffd20 0x10>;
746 reg = <0xfffffd40 0x10>;
757 reg = <0xfffffd50 0x10>;
764 reg = <0x00500000 0x100000>;
777 reg = <0x10000000 0x80000000>;
778 ranges = <0x0 0x0 0x10000000 0x10000000
779 0x1 0x0 0x20000000 0x10000000
780 0x2 0x0 0x30000000 0x10000000
781 0x3 0x0 0x40000000 0x10000000
782 0x4 0x0 0x50000000 0x10000000
783 0x5 0x0 0x60000000 0x10000000
784 0x6 0x0 0x70000000 0x10000000
785 0x7 0x0 0x80000000 0x10000000>;
799 i2c_gpio0: i2c-gpio-0 {
808 #size-cells = <0>;
810 pinctrl-0 = <&pinctrl_i2c_gpio0>;