Lines Matching +full:0 +full:xfffffe00
43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
54 reg = <0x20000000 0x04000000>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
67 clock-frequency = <0>;
73 reg = <0x00200000 0x4000>;
76 ranges = <0 0x00200000 0x4000>;
95 reg = <0xfffff000 0x200>;
101 reg = <0xffffff00 0x100>;
106 reg = <0xfffffc00 0x100>;
115 reg = <0xfffffd00 0x100>;
126 reg = <0xfffffe00 0x40>;
135 #size-cells = <0>;
136 reg = <0xfffa0000 0x100>;
137 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
138 18 IRQ_TYPE_LEVEL_HIGH 0
139 19 IRQ_TYPE_LEVEL_HIGH 0>;
147 #size-cells = <0>;
148 reg = <0xfffa4000 0x100>;
149 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
150 21 IRQ_TYPE_LEVEL_HIGH 0
151 22 IRQ_TYPE_LEVEL_HIGH 0>;
158 reg = <0xfffb8000 0x4000>;
161 pinctrl-0 = <&pinctrl_twi>;
164 #size-cells = <0>;
170 reg = <0xfffb4000 0x4000>;
171 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
175 #size-cells = <0>;
181 reg = <0xfffd0000 0x4000>;
184 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
192 reg = <0xfffd4000 0x4000>;
195 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
203 reg = <0xfffd8000 0x4000>;
206 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
214 reg = <0xfffbc000 0x4000>;
218 pinctrl-0 = <&pinctrl_macb_rmii>;
228 ranges = <0xfffff400 0xfffff400 0x800>;
232 0xffffffff 0xffffffff /* pioA */
233 0xffffffff 0x083fffff /* pioB */
234 0xffff3fff 0x00000000 /* pioC */
235 0x03ff87ff 0x0fffff80 /* pioD */
240 pinctrl_dbgu: dbgu-0 {
248 pinctrl_uart0: uart0-0 {
254 pinctrl_uart0_cts: uart0_cts-0 {
259 pinctrl_uart0_rts: uart0_rts-0 {
266 pinctrl_uart1: uart1-0 {
272 pinctrl_uart1_rts: uart1_rts-0 {
277 pinctrl_uart1_cts: uart1_cts-0 {
282 pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
288 pinctrl_uart1_dcd: uart1_dcd-0 {
293 pinctrl_uart1_ri: uart1_ri-0 {
300 pinctrl_uart2: uart2-0 {
306 pinctrl_uart2_rts: uart2_rts-0 {
311 pinctrl_uart2_cts: uart2_cts-0 {
318 pinctrl_uart3: uart3-0 {
324 pinctrl_uart3_rts: uart3_rts-0 {
326 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
329 pinctrl_uart3_cts: uart3_cts-0 {
336 pinctrl_nand: nand-0 {
344 pinctrl_macb_rmii: macb_rmii-0 {
358 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
372 pinctrl_mmc0_clk: mmc0_clk-0 {
377 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
383 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
390 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
396 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
405 pinctrl_ssc0_tx: ssc0_tx-0 {
407 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
412 pinctrl_ssc0_rx: ssc0_rx-0 {
421 pinctrl_ssc1_tx: ssc1_tx-0 {
428 pinctrl_ssc1_rx: ssc1_rx-0 {
437 pinctrl_ssc2_tx: ssc2_tx-0 {
444 pinctrl_ssc2_rx: ssc2_rx-0 {
453 pinctrl_twi: twi-0 {
459 pinctrl_twi_gpio: twi_gpio-0 {
467 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
471 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
475 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
479 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
483 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
487 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
491 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
495 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
499 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
505 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
509 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
513 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
517 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
521 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
525 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
529 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
533 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
537 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
543 pinctrl_spi0: spi0-0 {
545 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
553 reg = <0xfffff400 0x200>;
564 reg = <0xfffff600 0x200>;
575 reg = <0xfffff800 0x200>;
586 reg = <0xfffffa00 0x200>;
598 reg = <0xfffff200 0x200>;
601 pinctrl-0 = <&pinctrl_dbgu>;
609 reg = <0xfffc0000 0x200>;
614 pinctrl-0 = <&pinctrl_uart0>;
622 reg = <0xfffc4000 0x200>;
627 pinctrl-0 = <&pinctrl_uart1>;
635 reg = <0xfffc8000 0x200>;
640 pinctrl-0 = <&pinctrl_uart2>;
648 reg = <0xfffcc000 0x200>;
653 pinctrl-0 = <&pinctrl_uart3>;
661 reg = <0xfffb0000 0x4000>;
670 #size-cells = <0>;
672 reg = <0xfffe0000 0x200>;
675 pinctrl-0 = <&pinctrl_spi0>;
686 reg = <0x40000000 0x10000000>;
690 pinctrl-0 = <&pinctrl_nand>;
693 0
701 reg = <0x00300000 0x100000>;
709 i2c-gpio-0 {
718 pinctrl-0 = <&pinctrl_twi_gpio>;
720 #size-cells = <0>;