Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 #include "armada-370-xp.dtsi"
18 #address-cells = <1>;
19 #size-cells = <1>;
22 compatible = "marvell,armada370", "marvell,armada-370-xp";
31 compatible = "marvell,armada370-mbus", "simple-bus";
35 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
39 compatible = "marvell,armada-370-pcie";
43 #address-cells = <3>;
44 #size-cells = <2>;
46 msi-parent = <&mpic>;
47 bus-range = <0x00 0xff>;
59 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
60 reg = <0x0800 0 0 0 0>;
61 #address-cells = <3>;
62 #size-cells = <2>;
63 #interrupt-cells = <1>;
66 bus-range = <0x00 0xff>;
67 interrupt-map-mask = <0 0 0 0>;
68 interrupt-map = <0 0 0 0 &mpic 58>;
69 marvell,pcie-port = <0>;
70 marvell,pcie-lane = <0>;
77 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
78 reg = <0x1000 0 0 0 0>;
79 #address-cells = <3>;
80 #size-cells = <2>;
81 #interrupt-cells = <1>;
84 bus-range = <0x00 0xff>;
85 interrupt-map-mask = <0 0 0 0>;
86 interrupt-map = <0 0 0 0 &mpic 62>;
87 marvell,pcie-port = <1>;
88 marvell,pcie-lane = <0>;
94 internal-regs {
95 L2: l2-cache@8000 {
96 compatible = "marvell,aurora-outer-cache";
97 reg = <0x08000 0x1000>;
98 cache-id-part = <0x100>;
99 cache-level = <2>;
100 cache-unified;
101 wt-override;
105 compatible = "marvell,armada-370-gpio",
106 "marvell,orion-gpio";
107 reg = <0x18100 0x40>, <0x181c0 0x08>;
108 reg-names = "gpio", "pwm";
110 gpio-controller;
111 #gpio-cells = <2>;
112 #pwm-cells = <2>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
120 compatible = "marvell,armada-370-gpio",
121 "marvell,orion-gpio";
122 reg = <0x18140 0x40>, <0x181c8 0x08>;
123 reg-names = "gpio", "pwm";
125 gpio-controller;
126 #gpio-cells = <2>;
127 #pwm-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <2>;
135 compatible = "marvell,armada-370-gpio",
136 "marvell,orion-gpio";
137 reg = <0x18180 0x40>;
139 gpio-controller;
140 #gpio-cells = <2>;
141 interrupt-controller;
142 #interrupt-cells = <2>;
147 systemc: system-controller@18200 {
148 compatible = "marvell,armada-370-xp-system-controller";
149 reg = <0x18200 0x100>;
152 gateclk: clock-gating-control@18220 {
153 compatible = "marvell,armada-370-gating-clock";
154 reg = <0x18220 0x4>;
156 #clock-cells = <1>;
159 coreclk: mvebu-sar@18230 {
160 compatible = "marvell,armada-370-core-clock";
161 reg = <0x18230 0x08>;
162 #clock-cells = <1>;
166 compatible = "marvell,armada370-thermal";
167 reg = <0x18300 0x4
173 reg = <0x18330 0x4>;
176 cpuconf: cpu-config@21000 {
177 compatible = "marvell,armada-370-cpu-config";
178 reg = <0x21000 0x8>;
181 audio_controller: audio-controller@30000 {
182 #sound-dai-cells = <1>;
183 compatible = "marvell,armada370-audio";
184 reg = <0x30000 0x4000>;
187 clock-names = "internal";
192 compatible = "marvell,orion-xor";
193 reg = <0x60800 0x100
211 compatible = "marvell,orion-xor";
212 reg = <0x60900 0x100
230 compatible = "marvell,armada-370-crypto";
231 reg = <0x90000 0x10000>;
232 reg-names = "regs";
235 clock-names = "cesa0";
236 marvell,crypto-srams = <&crypto_sram>;
237 marvell,crypto-sram-size = <0x7e0>;
241 crypto_sram: sa-sram {
242 compatible = "mmio-sram";
243 reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
244 reg-names = "sram";
246 #address-cells = <1>;
247 #size-cells = <1>;
257 idle-sram@0 {
258 reg = <0x0 0x20>;
270 pinctrl-0 = <&uart0_pins>;
271 pinctrl-names = "default";
275 pinctrl-0 = <&uart1_pins>;
276 pinctrl-names = "default";
280 reg = <0x11000 0x20>;
284 reg = <0x11100 0x20>;
288 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
292 compatible = "marvell,armada-370-timer";
297 compatible = "marvell,armada-370-wdt";
310 compatible = "marvell,armada-370-neta";
314 compatible = "marvell,armada-370-neta";
318 compatible = "marvell,mv88f6710-pinctrl";
320 spi0_pins1: spi0-pins1 {
332 spi1_pins: spi1-pins {
338 uart0_pins: uart0-pins {
343 uart1_pins: uart1-pins {
348 sdio_pins1: sdio-pins1 {
354 sdio_pins2: sdio-pins2 {
360 sdio_pins3: sdio-pins3 {
366 i2c0_pins: i2c0-pins {
371 i2s_pins1: i2s-pins1 {
378 i2s_pins2: i2s-pins2 {
385 mdio_pins: mdio-pins {
390 ge0_rgmii_pins: ge0-rgmii-pins {
397 ge1_rgmii_pins: ge1-rgmii-pins {
410 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
411 pinctrl-0 = <&spi0_pins1>;
412 pinctrl-names = "default";
416 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
417 pinctrl-0 = <&spi1_pins>;
418 pinctrl-names = "default";