Lines Matching full:r0
79 mov r0, \val
84 mov r0, \val
231 mov r0, #0x17 @ angel_SWIreason_EnterSVC
235 safe_svcmode_maskall r0
283 mov r0, pc
284 cmp r0, r4
285 ldrcc r0, .Lheadroom
286 addcc r0, r0, pc
287 cmpcc r4, r0
291 restart: adr r0, LC1
292 ldr sp, [r0]
293 ldr r6, [r0, #4]
294 add sp, sp, r0
295 add r6, r6, r0
369 mov r0, r8
379 cmp r0, #1
380 sub r0, r4, #TEXT_OFFSET
381 bic r0, r0, #1
382 add r0, r0, #0x100
464 mrs r0, spsr
465 and r0, r0, #MODE_MASK
466 cmp r0, #HYP_MODE
476 0: adr r0, 0b
479 add r0, r0, r1
480 sub r0, r0, r5
481 add r0, r0, r10
506 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
508 stmdb r9!, {r0 - r3, r10 - r12, lr}
514 mov r0, r9 @ start of relocated zImage
518 badr r0, restart
519 add r0, r0, r6
520 mov pc, r0
523 adr r0, LC0
524 ldmia r0, {r1, r2, r3, r11, r12}
525 sub r0, r0, r1 @ calculate the delta offset
529 * r0 = delta
540 orrs r1, r0, r5
543 add r11, r11, r0
544 add r12, r12, r0
552 add r2, r2, r0
553 add r3, r3, r0
560 add r1, r1, r0 @ This fixes up C references
581 addlo r1, r1, r0 @ table. This fixes up the
587 not_relocated: mov r0, #0
588 1: str r0, [r2], #4 @ clear bss
589 str r0, [r2], #4
590 str r0, [r2], #4
591 str r0, [r2], #4
611 mov r0, r4
619 mov r0, r4 @ start of inflated image
620 add r1, r1, r0 @ end of inflated image
625 mrs r0, spsr @ Get saved CPU boot mode
626 and r0, r0, #MODE_MASK
627 cmp r0, #HYP_MODE @ if not booted in HYP mode...
631 ldr r0, [r12]
632 add r0, r0, r12
667 params: ldr r0, =0x10000100 @ params_phys for RPC
704 * r0, r1, r2, r3, r9, r10, r12 corrupted
717 mov r0, #0x3f @ 4G, the whole
718 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
719 mcr p15, 0, r0, c6, c7, 1
721 mov r0, #0x80 @ PR7
722 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
723 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
724 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
726 mov r0, #0xc000
727 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
728 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
730 mov r0, #0
731 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
732 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
733 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
734 mrc p15, 0, r0, c1, c0, 0 @ read control reg
736 orr r0, r0, #0x002d @ .... .... ..1. 11.1
737 orr r0, r0, #0x1000 @ ...1 .... .... ....
739 mcr p15, 0, r0, c1, c0, 0 @ write control reg
741 mov r0, #0
742 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
743 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
747 mov r0, #0x3f @ 4G, the whole
748 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
750 mov r0, #0x80 @ PR7
751 mcr p15, 0, r0, c2, c0, 0 @ cache on
752 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
754 mov r0, #0xc000
755 mcr p15, 0, r0, c5, c0, 0 @ access permission
757 mov r0, #0
758 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
763 mrc p15, 0, r0, c1, c0, 0 @ read control reg
765 orr r0, r0, #0x000d @ .... .... .... 11.1
767 mov r0, #0
768 mcr p15, 0, r0, c1, c0, 0 @ write control reg
771 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
787 mov r0, r3
788 mov r9, r0, lsr #18
799 str r1, [r0], #4 @ 1:1 mapping
801 teq r0, r2
814 add r0, r3, r2, lsl #2
815 str r1, [r0], #4
817 str r1, [r0]
824 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
825 bic r0, r0, #2 @ A (no unaligned access fault)
826 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
827 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
832 mov r0, #4 @ put dcache in WT mode
833 mcr p15, 7, r0, c15, c0, 0
841 mov r0, #0
842 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
843 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
844 mrc p15, 0, r0, c1, c0, 0 @ read control reg
845 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
846 orr r0, r0, #0x0030
847 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
849 mov r0, #0
850 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
862 mov r0, #0
863 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
865 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
867 mrc p15, 0, r0, c1, c0, 0 @ read control reg
868 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
869 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
870 orr r0, r0, #0x003c @ write buffer
871 bic r0, r0, #2 @ A (no unaligned access fault)
872 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
875 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
877 orrne r0, r0, #1 @ MMU enabled
885 mcr p15, 0, r0, c7, c5, 4 @ ISB
886 mcr p15, 0, r0, c1, c0, 0 @ load control register
887 mrc p15, 0, r0, c1, c0, 0 @ and read it back
888 mov r0, #0
889 mcr p15, 0, r0, c7, c5, 4 @ ISB
896 mov r0, #0
897 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
898 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
899 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
900 mrc p15, 0, r0, c1, c0, 0 @ read control reg
901 orr r0, r0, #0x1000 @ I-cache enable
903 mov r0, #0
904 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
910 orr r0, r0, #0x000d @ Write buffer, mmu
917 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
918 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
919 sub pc, lr, r0, lsr #32 @ properly flush pipeline
1138 * r0, r1, r2, r3, r9, r12 corrupted
1147 mrc p15, 0, r0, c1, c0
1148 bic r0, r0, #0x000d
1149 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1150 mov r0, #0
1151 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1152 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1153 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1157 mrc p15, 0, r0, c1, c0
1158 bic r0, r0, #0x000d
1159 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1160 mov r0, #0
1161 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1166 mrc p15, 0, r0, c1, c0
1167 bic r0, r0, #0x000d
1168 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1169 mov r0, #0
1170 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1171 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1176 mrc p15, 0, r0, c1, c0
1178 bic r0, r0, #0x000d
1180 bic r0, r0, #0x000c
1182 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1183 mov r0, #0
1185 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1187 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1188 mcr p15, 0, r0, c7, c10, 4 @ DSB
1189 mcr p15, 0, r0, c7, c5, 4 @ ISB
1196 * r0 = start address
1259 bic r0, r0, r2 @ round down start to line size
1262 0: cmp r0, r11 @ finished?
1264 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1265 add r0, r0, r1
1279 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1280 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1335 @ phex corrupts {r0, r1, r2, r3}
1340 movmi r0, r3
1342 and r2, r0, #15
1343 mov r0, r0, lsr #4
1350 @ puts corrupts {r0, r1, r2, r3}
1352 1: ldrb r2, [r0], #1
1362 teq r0, #0
1365 @ putc corrupts {r0, r1, r2, r3}
1367 mov r2, r0
1368 loadsp r3, r1, r0
1369 mov r0, #0
1372 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1373 memdump: mov r12, r0
1376 2: mov r0, r11, lsl #2
1377 add r0, r0, r12
1380 mov r0, #':'
1382 1: mov r0, #' '
1384 ldr r0, [r12, r11, lsl #2]
1387 and r0, r11, #7
1388 teq r0, #3
1389 moveq r0, #' '
1391 and r0, r11, #7
1393 teq r0, #7
1395 mov r0, #'\n'
1422 mov r0, #0 @ must be 0
1433 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1434 bic r0, r0, #0x5 @ disable MMU and caches
1435 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1440 mov r4, r0 @ preserve image base
1443 ARM( adrl r0, call_cache_fn )
1444 THUMB( adr r0, call_cache_fn )
1458 mrs r0, cpsr @ get the current mode
1459 msr spsr_cxsf, r0 @ record boot mode
1460 and r0, r0, #MODE_MASK @ are we running in HYP mode?
1461 cmp r0, #HYP_MODE
1478 adr r0, __hyp_reentry_vectors
1479 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1491 msr spsr_cxsf, r0 @ record boot mode
1496 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
1497 tst r0, #0x1 @ MMU enabled?
1501 mov r0, r8 @ DT start
1505 adr r0, 0f @ switch to our stack
1506 ldr sp, [r0]
1507 add sp, sp, r0