boot/compressed/head.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  *  Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
14  AR_CLASS(	.arch	armv7-a	)
15  M_CLASS(	.arch	armv7-m	)
99 		kputc	#'-'
103 		kputc	#'-'
108 		kputc	#'-'
152 		 * in little-endian form.
224 		 * Booting from Angel - need to enter SVC mode and disable
241 		 * be needed here - is there an Angel SWI call for this?
259 		 * different platforms - we have chosen 128MB to allow
279 		 * That means r4 < pc || r4 - 16k page directory > &_end.
304 		 * With ZBOOT_ROM the bss/stack is non relocatable,
320  *   r10 = end of this image, including  bss/stack/malloc space if non XIP
358 		/* preserve 64-bit alignment */
414 		/* preserve 64-bit alignment */
429  *   r10 = end of this image, including  bss/stack/malloc space if non XIP
431  *   r4 - 16k page directory >= r10 -> OK
432  *   r4 + image length <= address of wont_overwrite -> OK
451 		 * Bump to the next 256-byte boundary with the size of
455 		add	r10, r10, #((reloc_code_end - restart + 256) & ~255)
472 		 * reference __hyp_stub_vectors in a PC-relative way.
477 		movw	r1, #:lower16:__hyp_stub_vectors - 0b
478 		movt	r1, #:upper16:__hyp_stub_vectors - 0b
506 1:		ldmdb	r6!, {r0 - r3, r10 - r12, lr}
508 		stmdb	r9!, {r0 - r3, r10 - r12, lr}
640 .L__hyp_reentry_vectors_offset:	.long	__hyp_reentry_vectors - .
652 		.size	LC0, . - LC0
655 LC1:		.word	.L_user_stack_end - LC1	@ sp
656 		.word	_edata - LC1		@ r6
657 		.size	LC1, . - LC1
660 		.word	_end - restart + 16384 + 1024*1024
663 		.long	(input_data_end - 4) - .
674  * dcache_line_size - get the minimum D-cache line size from the CTR register
675  * on ARMv7.
722 		mcr	p15, 0, r0, c2, c0, 0	@ D-cache on
723 		mcr	p15, 0, r0, c2, c0, 1	@ I-cache on
724 		mcr	p15, 0, r0, c3, c0, 0	@ write-buffer on
727 		mcr	p15, 0, r0, c5, c0, 1	@ I-access permission
728 		mcr	p15, 0, r0, c5, c0, 0	@ D-access permission
732 		mcr	p15, 0, r0, c7, c5, 0	@ flush(inval) I-Cache
733 		mcr	p15, 0, r0, c7, c6, 0	@ flush(inval) D-Cache
742 		mcr	p15, 0, r0, c7, c5, 0	@ flush(inval) I-Cache
743 		mcr	p15, 0, r0, c7, c6, 0	@ flush(inval) D-Cache
752 		mcr	p15, 0, r0, c3, c0, 0	@ write-buffer on
797 		orrlo	r1, r1, #0x10		@ Set XN|U for non-RAM
845 		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement
847  ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables
869 		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement
875  ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables
879 		bic     r6, r6, #1 << 31        @ 32-bit translation system
901 		orr	r0, r0, #0x1000		@ I-cache enable
912 		mov	r1, #-1
943 		 * On v7-M the processor id is located in the V7M_SCB_CPUID
945 		 * v7-M (if existant at all) we just return early here.
948 		 * use cp15 registers that are not implemented on v7-M.
966  *   - CPU ID match
967  *   - CPU ID mask
968  *   - 'cache on' method instruction
969  *   - 'cache off' method instruction
970  *   - 'cache flush' method instruction
1018 		.word	0x41069260		@ ARM926EJ-S (v5TEJ)
1121 		.size	proc_types, . - proc_types
1124 		 * If you get a "non-constant expression in ".if" statement"
1129 		.if (. - proc_types) % PROC_ENTRY_SIZE != 0
1152 		mcr	p15, 0, r0, c7, c6, 0	@ flush D-Cache
1153 		mcr	p15, 0, r0, c7, c5, 0	@ flush I-Cache
1251 		tst	r10, #0xf << 16		@ hierarchical cache (ARMv7)
1333 		.size	phexbuf, . - phexbuf
1452 		@ 32-bit addressable DRAM mapped 1:1 using short descriptors.
1455 		@ U-Boot might decide to enter the EFI stub in HYP mode
1513 0:		.long	.L_user_stack_end - .