boot/compressed/head.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  *  Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
14  AR_CLASS(	.arch	armv7-a	)
15  M_CLASS(	.arch	armv7-m	)
99 		kputc	#'-'
103 		kputc	#'-'
108 		kputc	#'-'
143 		mcr	p15, 0, \reg, c1, c0, 0	@ write SCTLR
152 		 * in little-endian form.
199  AR_CLASS(	sub	pc, pc, #3	)	@ A/R: switch to Thumb2 mode
224 		 * Booting from Angel - need to enter SVC mode and disable
241 		 * be needed here - is there an Angel SWI call for this?
259 		 * different platforms - we have chosen 128MB to allow
269 		mov	r4, pc
279 		 * That means r4 < pc || r4 - 16k page directory > &_end.
283 		mov	r0, pc
286 		addcc	r0, r0, pc
341 		 * and folded into the former here. No GOT fixup has occurred
358 		/* preserve 64-bit alignment */
375 		 * If returned value is 1, there is no ATAG at the location
414 		/* preserve 64-bit alignment */
431  *   r4 - 16k page directory >= r10 -> OK
432  *   r4 + image length <= address of wont_overwrite -> OK
451 		 * Bump to the next 256-byte boundary with the size of
455 		add	r10, r10, #((reloc_code_end - restart + 256) & ~255)
472 		 * reference __hyp_stub_vectors in a PC-relative way.
477 		movw	r1, #:lower16:__hyp_stub_vectors - 0b
478 		movt	r1, #:upper16:__hyp_stub_vectors - 0b
506 1:		ldmdb	r6!, {r0 - r3, r10 - r12, lr}
508 		stmdb	r9!, {r0 - r3, r10 - r12, lr}
520 		mov	pc, r0
640 .L__hyp_reentry_vectors_offset:	.long	__hyp_reentry_vectors - .
652 		.size	LC0, . - LC0
655 LC1:		.word	.L_user_stack_end - LC1	@ sp
656 		.word	_edata - LC1		@ r6
657 		.size	LC1, . - LC1
660 		.word	_end - restart + 16384 + 1024*1024
663 		.long	(input_data_end - 4) - .
668 		mov	pc, lr
674  * dcache_line_size - get the minimum D-cache line size from the CTR register
722 		mcr	p15, 0, r0, c2, c0, 0	@ D-cache on
723 		mcr	p15, 0, r0, c2, c0, 1	@ I-cache on
724 		mcr	p15, 0, r0, c3, c0, 0	@ write-buffer on
727 		mcr	p15, 0, r0, c5, c0, 1	@ I-access permission
728 		mcr	p15, 0, r0, c5, c0, 0	@ D-access permission
731 		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
732 		mcr	p15, 0, r0, c7, c5, 0	@ flush(inval) I-Cache
733 		mcr	p15, 0, r0, c7, c6, 0	@ flush(inval) D-Cache
739 		mcr	p15, 0, r0, c1, c0, 0	@ write control reg
742 		mcr	p15, 0, r0, c7, c5, 0	@ flush(inval) I-Cache
743 		mcr	p15, 0, r0, c7, c6, 0	@ flush(inval) D-Cache
744 		mov	pc, lr
752 		mcr	p15, 0, r0, c3, c0, 0	@ write-buffer on
768 		mcr	p15, 0, r0, c1, c0, 0	@ write control reg
772 		mov	pc, lr
797 		orrlo	r1, r1, #0x10		@ Set XN|U for non-RAM
806  * so there is no map overlap problem for up to 1 MB compressed kernel.
811 		mov	r2, pc
818 		mov	pc, lr
825 		bic	r0, r0, #2		@ A (no unaligned access fault)
827 		mcr	p15, 0, r0, c1, c0, 0	@ write SCTLR
842 		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
845 		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement
847  ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables
852 		mov	pc, r12
863 		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
869 		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement
870 		orr	r0, r0, #0x003c		@ write buffer
871 		bic	r0, r0, #2		@ A (no unaligned access fault)
875  ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables
879 		bic     r6, r6, #1 << 31        @ 32-bit translation system
890 		mov	pc, r12
898 		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
901 		orr	r0, r0, #0x1000		@ I-cache enable
905 		mov	pc, r12
910 		orr	r0, r0, #0x000d		@ Write buffer, mmu
912 		mov	r1, #-1
919 		sub	pc, lr, r0, lsr #32	@ properly flush pipeline
943 		 * On v7-M the processor id is located in the V7M_SCB_CPUID
945 		 * v7-M (if existant at all) we just return early here.
948 		 * use cp15 registers that are not implemented on v7-M.
958  ARM(		addeq	pc, r12, r3		) @ call cache function
960  THUMB(		moveq	pc, r12			) @ call cache function
966  *   - CPU ID match
967  *   - CPU ID mask
968  *   - 'cache on' method instruction
969  *   - 'cache off' method instruction
970  *   - 'cache flush' method instruction
983 		mov	pc, lr
985 		mov	pc, lr
987 		mov	pc, lr
992 		mov	pc, lr
994 		mov	pc, lr
996 		mov	pc, lr
1003 		mov	pc, lr
1018 		.word	0x41069260		@ ARM926EJ-S (v5TEJ)
1026 		mov	pc, lr
1028 		mov	pc, lr
1030 		mov	pc, lr
1114 		mov	pc, lr
1116 		mov	pc, lr
1118 		mov	pc, lr
1121 		.size	proc_types, . - proc_types
1124 		 * If you get a "non-constant expression in ".if" statement"
1129 		.if (. - proc_types) % PROC_ENTRY_SIZE != 0
1151 		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
1152 		mcr	p15, 0, r0, c7, c6, 0	@ flush D-Cache
1153 		mcr	p15, 0, r0, c7, c5, 0	@ flush I-Cache
1154 		mov	pc, lr
1162 		mov	pc, lr
1173 		mov	pc, lr
1190 		mov	pc, lr
1211 		movne	pc, lr
1226 		mov	pc, lr
1230 		movne	pc, lr
1235 		mov	pc, lr
1244 		mov	pc, lr
1272 		mov	pc, lr
1276 		movne	pc, lr
1281 		mov	pc, lr
1285 		movne	pc, lr
1302 		mov	r1, pc
1315 		mov	pc, lr
1320 		movne	pc, lr
1323 		mov	pc, lr
1333 		.size	phexbuf, . - phexbuf
1354 		moveq	pc, lr
1364 		mov	pc, lr
1399 		mov	pc, r10
1425  ARM(		mov	pc, r4		)	@ call kernel
1435 		mcr	p15, 4, r0, c1, c0, 0	@ write HSCTLR
1452 		@ 32-bit addressable DRAM mapped 1:1 using short descriptors.
1455 		@ U-Boot might decide to enter the EFI stub in HYP mode
1513 0:		.long	.L_user_stack_end - .