include/asm/pgtable.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6  *  -Folded PAGE_PRESENT (used by VM) and PAGE_VALID (used by MMU) into 1.
8  *     VALID marks a TLB entry exists and it will only happen if PRESENT
9  *  - Utilise some unused free bits to confine PTE flags to 12 bits
10  *     This is a must for 4k pg-sz
12  * vineetg: Mar 2011 - changes to accommodate MMU TLB Page Descriptor mods
13  *  -TLB Locking never really existed, except for initial specs
14  *  -SILENT_xxx not needed for our port
15  *  -Per my request, MMU V3 changes the layout of some of the bits
16  *     to avoid a few shifts in TLB Miss handlers.
19  *  -PGD entry no longer contains any flags. If empty it is 0, otherwise has
20  *   Pg-Tbl ptr. Thus pmd_present(), pmd_valid(), pmd_set( ) become simpler
23  *  -Switched form 8:11:13 split for page table lookup to 11:8:13
24  *  -this speeds up page table allocation itself as we now have to memset 1K
26  * -TODO: Right now page table alloc is 8K and rest 7K is unused
36 #include <asm-generic/pgtable-nopmd.h>
43  * ARC700 MMU only deals with softare managed TLB entries.
45  * suited to that (uniqueness). Hence some are not implemented in the TLB and
46  * some have different value in TLB.
51  *      (saves some bit shift ops in TLB Miss hdlrs)
64 #define _PAGE_PRESENT       (1<<10)	/* TLB entry is valid (H) */
77 #define _PAGE_WTHRU         (1<<7)	/* Page cache mode write-thru (H) */
81 #define _PAGE_PRESENT       (1<<9)	/* TLB entry is valid (H) */
84 #define _PAGE_HW_SZ         (1<<10)	/* Page Size indicator (H): 0 normal, 1 super */
88 					   usable for shared TLB entries (H) */
123  * user vaddr space - visible in all addr spaces, but kernel mode only
124  * Thus Global, all-kernel-access, no-user-access, cached
131 /* Masks for actual TLB "PD"s */
155  *      -Write implies Read:   W => R
156  *      -Execute implies Read: X => R
158  *  2. Pvt Writable doesn't have Write Enabled initially: Pvt-W => !W
164 #define __P010  PAGE_U_R	/* Pvt-W => !W */
165 #define __P011  PAGE_U_R	/* Pvt-W => !W */
168 #define __P110  PAGE_U_X_R	/* Pvt-W => !W and X => R */
169 #define __P111  PAGE_U_X_R	/* Pvt-W => !W */
184  * -------------------------------------------------------
185  * |               | <------------ PGDIR_SHIFT ----------> |
187  * | BITS_FOR_PGD  |  BITS_FOR_PTE  | <-- PAGE_SHIFT --> |
188  * -------------------------------------------------------
190  *       |                  |                --> off in page frame
191  *       |                  ---> index into Page Table
192  *       ----> index into Page Directory
194  * In a single page size configuration, only PAGE_SHIFT is fixed
197  *  - PGDIR_SHIFT 21  -> 11:8:13 address split
198  *  - PGDIR_SHIFT 24  -> 8:11:13 address split
216 #define BITS_FOR_PTE	(PGDIR_SHIFT - PAGE_SHIFT)
217 #define BITS_FOR_PGD	(32 - PGDIR_SHIFT)
220 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
245 	pr_crit("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
247 	pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
326  * Thus task->mm->pgd (3 pointer dereferences, cache misses etc simply
349  * We reserve 13 bits for 5-bit @type, keeping bits 12-5 zero, ensuring that
366  * remap a physical page `pfn' of size `size' with page protection `prot'