1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6  *  -Refactored get_new_mmu_context( ) to only handle live-mm.
7  *   retiring-mm handled in other hooks
10  *  -Major rewrite of Core ASID allocation routine get_new_mmu_context
22 #include <asm-generic/mm_hooks.h>
26  * ARC MMU provides 8-bit ASID (0..255) to TAG TLB entries, allowing entries
27  * with same vaddr (different tasks) to co-exit. This provides for
28  * "Fast Context Switch" i.e. no TLB flush on ctxt-switch
30  * Linux assigns each task a unique ASID. A simple round-robin allocation
37  * The 32 bit @asid_cpu (and mm->asid) have 8 bits MMU PID and rest 24 bits
39  * automagically increments the generation when lower 8 bits rollover.
42 #define MM_CTXT_ASID_MASK	0x000000ff /* MMU PID reg :8 bit PID */
48 #define asid_mm(mm, cpu)	mm->context.asid[cpu]  argument
49 #define hw_pid(mm, cpu)		(asid_mm(mm, cpu) & MM_CTXT_ASID_MASK)  argument
52 #define asid_cpu(cpu)		per_cpu(asid_cache, cpu)  argument
60 	const unsigned int cpu = smp_processor_id();  in get_new_mmu_context()  local
66 	 * Move to new ASID if it was not from current alloc-cycle/generation.  in get_new_mmu_context()
67 	 * This is done by ensuring that the generation bits in both mm->ASID  in get_new_mmu_context()
68 	 * and cpu's ASID counter are exactly same.  in get_new_mmu_context()
75 	if (!((asid_mm(mm, cpu) ^ asid_cpu(cpu)) & MM_CTXT_CYCLE_MASK))  in get_new_mmu_context()
79 	if (unlikely(!(++asid_cpu(cpu) & MM_CTXT_ASID_MASK))) {  in get_new_mmu_context()
84 		 * Above check for rollover of 8 bit ASID in 32 bit container.  in get_new_mmu_context()
88 		if (!asid_cpu(cpu))  in get_new_mmu_context()
89 			asid_cpu(cpu) = MM_CTXT_FIRST_CYCLE;  in get_new_mmu_context()
93 	asid_mm(mm, cpu) = asid_cpu(cpu);  in get_new_mmu_context()
96 	write_aux_reg(ARC_REG_PID, hw_pid(mm, cpu) | MMU_ENABLE);  in get_new_mmu_context()
132 	const int cpu = smp_processor_id();  in switch_mm()  local
136 	 * for the switched-out task, unlike some other arches.  in switch_mm()
138 	 * it to CPUs where a task once ran-on, could cause stale TLB entry  in switch_mm()
139 	 * re-use, specially for a multi-threaded task.  in switch_mm()
141 	 *      For a non-aggregating mm_cpumask, IPI not sent C1, and if T1  in switch_mm()
142 	 *      were to re-migrate to C1, it could access the unmapped region  in switch_mm()
145 	cpumask_set_cpu(cpu, mm_cpumask(next));  in switch_mm()
148 	/* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */  in switch_mm()
149 	write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd);  in switch_mm()
164 /* it seemed that deactivate_mm( ) is a reasonable place to do book-keeping
165  * for retiring-mm. However destroy_context( ) still needs to do that because
168  * there is a good chance that task gets sched-out/in, making it's ASID valid