alpha/lib/ev6-memchr.S

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * arch/alpha/lib/ev6-memchr.S
5  * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
9  *    - memory accessed as aligned quadwords only
10  *    - uses cmpbge to compare 8 bytes in parallel
11  *    - does binary search to find 0 byte in last
18  *    - only minimum number of quadwords may be accessed
19  *    - the third argument is an unsigned long
24  *	ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
26  *	E	- either cluster
27  *	U	- upper subcluster; U0 - subcluster U0; U1 - subcluster U1
28  *	L	- lower subcluster; L0 - subcluster L0; L1 - subcluster L1
42 	# Hack -- if someone passes in (size_t)-1, hoping to just
45 	# that we will never have a 56-bit address space, cropping
49         ldq_u   $1, 0($16)	# L : load first quadword Latency=3
50 	and	$17, 0xff, $17	# E : L L U U : 00000000000000ch
52 	insbl	$17, 1, $2	# U : 000000000000ch00
54 	or	$2, $17, $17	# E : 000000000000chch
55         lda     $3, -1($31)	# E : U L L U
57 	sll	$17, 16, $2	# U : 00000000chch0000
58 	addq	$16, $5, $5	# E : Max search address
59 	or	$2, $17, $17	# E : 00000000chchchch
60 	sll	$17, 32, $2	# U : U L L U : chchchch00000000
62 	or	$2, $17, $17	# E : chchchchchchchch
63 	extql	$1, $16, $7	# U : $7 is upper bits
65 	ldq_u	$6, -1($5)	# L : L U U L : eight or less bytes to search Latency=3
67 	extqh	$6, $16, $6	# U : 2 cycle stall for $6
68 	mov	$16, $0		# E :
70 	or	$7, $6, $1	# E : L U L U $1 = quadword starting at $16
78         xor	$17, $1, $1	# E :
124 	# searched.  $16 may not be aligned.
127 	andnot	$16, 0x7, $0	# E :
128         insqh   $3, $16, $2	# U : $2 = 0000ffffffffffff ($16<0:2> ff)
129         xor	$1, $17, $1	# E :
147 	subq	$18, $0, $4	# E : $4 <- nr quads to be processed
156 	xor	$17, $4, $2	# E :
166 	xor	$17, $1, $2	# E :
181 $final:	subq	$5, $0, $18	# E : $18 <- number of bytes left to do