Lines Matching +full:cache +full:- +full:controller

9      1. With and without an Coherent Cache Controller which
12      2. With and without An Intelligent Memory Controller which
15 The Core comes up with a default value of for the three types of cache ops::
19 On the FPGA Cards we typically simulate an Intelligent Memory controller
21 Memory controller we let it to the atomic operations internally while
22 doing a Cached (WB) transaction and use the Memory RCW for un-cached
25 For systems without an coherent cache controller, non-MX, we always
26 use the memory controllers RCW, thought non-MX controlers likely
29 CUSTOMER-WARNING:
35 with the cache being bypassed; for example studying cache alias problems.
45   Values     WB - Write Back         WT - Write Thru         BY - Bypass