x86/x86_64/boot-options.rst

1 .. SPDX-License-Identifier: GPL-2.0
15 		Disable machine check
17 		Disable CMCI(Corrected Machine Check Interrupt) that
30 		Disable features for corrected errors, e.g. polling timer
39 		Do not opt-in to Local MCE delivery. Use legacy method
49 		Disable boot machine check logging.
57 		Can be also set using sysfs which is preferable.
60 		to disable.
62 		Don't overwrite the bios-set CMCI threshold. This boot option
69 		Force-enable recoverable machine check code paths
80 	Use IO-APIC. Default
83 	Don't use the IO-APIC.
92 	See Documentation/x86/i386/IO-APIC.rst
98 	Don't check the IO-APIC timer. This can work around
155      Don't stop other CPUs on reboot. This can make reboot more reliable
165       Disable
177     Don't parse the HMAT table for NUMA setup, or soft-reserved memory
202     Disable out of spec ACPI workarounds.
208     Disable firmware first mode for corrected errors. This
224   pci=assign-busses
235 Multiple x86-64 PCI-DMA mapping implementations exist, for example:
239       Kernel boot message: "PCI-DMA: Disabling IOMMU"
242       Kernel boot message: "PCI-DMA: using GART IOMMU"
244    3. <arch/x86_64/kernel/pci-swiotlb.c> : Software IOMMU implementation. Used
247       Kernel boot message: "PCI-DMA: Using software bounce buffering
250    4. <arch/x86_64/pci-calgary.c> : IBM Calgary hardware IOMMU. Used in IBM
253       Kernel boot message: "PCI-DMA: Using Calgary IOMMU"
272       Intel machines). This can be used to prevent the usage
289       Do scatter-gather (SG) merging. Implies "force" (experimental).
291       Don't do scatter-gather (SG) merging.
317       32MB; the largest, 8MB table, can cover an IO space of 4GB.
322     calgary=[disable=<PCI bus number>]
323       Disable translation on a given PHB. For
324       example, the built-in graphics adapter resides on the first bridge