Documentation/vm/hmm.rst

4 Heterogeneous Memory Management (HMM)
7 Provide infrastructure and helpers to integrate non-conventional memory (device
8 memory like GPU on board memory) into regular kernel path, with the cornerstone
9 of this being specialized struct page for such memory (see sections 5 to 7 of
12 HMM also provides optional helpers for SVM (Share Virtual Memory), i.e.,
13 allowing a device to transparently access program addresses coherently with
15 for the device. This is becoming mandatory to simplify the use of advanced
16 heterogeneous computing where GPU, DSP, or FPGA are used to perform various
20 related to using device specific memory allocators. In the second section, I
21 expose the hardware limitations that are inherent to many platforms. The third
23 CPU page-table mirroring works and the purpose of HMM in this context. The
24 fifth section deals with how device memory is represented inside the kernel.
30 Problems of using a device specific memory allocator
33 Devices with a large amount of on board memory (several gigabytes) like GPUs
34 have historically managed their memory through dedicated driver specific APIs.
35 This creates a disconnect between memory allocated and managed by a device
36 driver and regular application memory (private anonymous, shared memory, or
37 regular file backed memory). From here on I will refer to this aspect as split
38 address space. I use shared address space to refer to the opposite situation:
39 i.e., one in which any application memory region can be used by a device
42 Split address space happens because devices can only access memory allocated
43 through a device specific API. This implies that all memory objects in a program
47 Concretely, this means that code that wants to leverage devices like GPUs needs
48 to copy objects between generically allocated memory (malloc, mmap private, mmap
49 share) and memory allocated through the device driver API (this still ends up
52 For flat data sets (array, grid, image, ...) this isn't too hard to achieve but
53 for complex data sets (list, tree, ...) it's hard to get right. Duplicating a
54 complex data set needs to re-map all the pointer relations between each of its
55 elements. This is error prone and programs get harder to debug because of the
60 might have to duplicate its input data set using the device specific memory
62 various memory copies.
64 Duplicating each library API to accept as input or output memory allocated by
65 each device specific allocator is not a viable option. It would lead to a
69 other languages too) it is now possible for the compiler to leverage GPUs and
71 are only do-able with a shared address space. It is also more reasonable to use
75 I/O bus, device memory characteristics
78 I/O buses cripple shared address spaces due to a few limitations. Most I/O
79 buses only allow basic memory access from device to main memory; even cache
80 coherency is often optional. Access to device memory from a CPU is even more
83 If we only consider the PCIE bus, then a device can access main memory (often
85 a limited set of atomic operations from the device on main memory. This is worse
87 memory and cannot perform atomic operations on it. Thus device memory cannot
88 be considered the same as regular memory from the kernel point of view.
91 and 16 lanes). This is 33 times less than the fastest GPU memory (1 TBytes/s).
92 The final limitation is latency. Access to main memory from the device has an
93 order of magnitude higher latency than when the device accesses its own memory.
95 Some platforms are developing new I/O buses or additions/modifications to PCIE
96 to address some of these limitations (OpenCAPI, CCIX). They mainly allow
97 two-way cache coherency between CPU and device and allow all atomic operations the
99 some major architectures are left without hardware solutions to these problems.
101 So for shared address space to make sense, not only must we allow devices to
102 access any memory but we must also permit any memory to be migrated to device
103 memory while the device is using it (blocking CPU access while it happens).
109 HMM intends to provide two main features. The first one is to share the address
111 address points to the same physical memory for any valid main memory address in
114 To achieve this, HMM offers a set of helpers to populate the device page table
116 not as easy as CPU page table updates. To update the device page table, you must
117 allocate a buffer (or use a pool of pre-allocated buffers) and write GPU
118 specific commands in it to perform the update (unmap, cache invalidations, and
120 why HMM provides helpers to factor out everything that can be while leaving the
121 hardware specific details to the device driver.
123 The second mechanism HMM provides is a new kind of ZONE_DEVICE memory that
124 allows allocating a struct page for each page of device memory. Those pages
126 main memory to device memory using existing migration mechanisms and everything
127 looks like a page that is swapped out to disk from the CPU point of view. Using a
129 mechanisms. Here again, HMM only provides helpers, first to hotplug new ZONE_DEVICE
130 memory for the device memory and second to perform migration. Policy decisions
131 of what and when to migrate is left to the device driver.
133 Note that any CPU access to a device page triggers a page fault and a migration
134 back to main memory. For example, when a page backing a given CPU address A is
135 migrated from a main memory page to a device page, then any CPU access to
136 address A triggers a page fault and initiates a migration back to main memory.
138 With these two features, HMM not only allows a device to mirror process address
140 leverages device memory by migrating the part of the data set that is actively being
147 Address space mirroring's main objective is to allow duplication of a range of
149 device driver that wants to mirror a process address space must start with the
157 During the ops->invalidate() callback the device driver must perform the
158 update action to the range (mark range read only, or fully unmap, etc.). The
161 When the device driver wants to populate a range of virtual addresses, it can
166 It will trigger a page fault on missing or read-only entries if write access is
171 entry in that array corresponds to an address in the virtual range. HMM
172 provides a set of flags to help the driver identify special CPU page table
176 aspect the driver must respect in order to keep things properly synchronized.
189       if (!mmget_not_zero(interval_sub->notifier.mm))
190           return -EFAULT;
198           if (ret == -EBUSY)
204       take_lock(driver->update);
206           release_lock(driver->update);
210       /* Use pfns array content to update device page table,
213       release_lock(driver->update);
217 The driver->update lock is the same lock that the driver takes inside its
219 mmu_interval_read_retry() to avoid any race with a concurrent CPU page table
226 fault or snapshot policy for the whole range instead of having to set them
232     range->default_flags = HMM_PFN_REQ_FAULT;
233     range->pfn_flags_mask = 0;
238 Now let's say the driver wants to do the same except for one page in the range for
239 which it wants to have write permission. Now driver set::
241     range->default_flags = HMM_PFN_REQ_FAULT;
242     range->pfn_flags_mask = HMM_PFN_REQ_WRITE;
243     range->pfns[index_of_write] = HMM_PFN_REQ_WRITE;
246 address == range->start + (index_of_write << PAGE_SHIFT) it will fault with
250 After hmm_range_fault completes the flag bits are set to the current state of
255 Represent and manage device memory from core kernel point of view
258 Several different designs were tried to support device memory. The first one
259 used a device specific data structure to keep information about migrated memory
260 and HMM hooked itself in various places of mm code to handle any access to
261 addresses that were backed by device memory. It turns out that this ended up
263 paths to be updated to understand this new kind of memory.
265 Most kernel code paths never try to access the memory behind a page
266 but only care about struct page contents. Because of this, HMM switched to
267 directly using struct page for device memory which left most kernel code paths
268 unaware of the difference. We only need to make sure that no one ever tries to
271 Migration to and from device memory
274 Because the CPU cannot access device memory directly, the device driver must
275 use hardware DMA or device specific load/store instructions to migrate data.
277 functions are designed to make drivers easier to write and to centralize common
280 Before migrating pages to device private memory, special device private
281 ``struct page`` need to be created. These will be used as special "swap"
282 page table entries so that a CPU process will fault if it tries to access
283 a page that has been migrated to device private memory.
293     pagemap.range.start = res->start;
294     pagemap.range.end = res->end;
304 be tied to a ``struct device``.
306 The overall migration steps are similar to migrating NUMA pages within system
307 memory (see :ref:`Page migration <page_migration>`) but the steps are split
312    The device driver has to pass a ``struct vm_area_struct`` to
313    migrate_vma_setup() so the mmap_read_lock() or mmap_write_lock() needs to
319    the pointer to migrate_vma_setup(). The ``args->flags`` field is used to
321    ``MIGRATE_VMA_SELECT_SYSTEM`` will only migrate system memory and
323    device private memory. If the latter flag is set, the ``args->pgmap_owner``
324    field is used to identify device private pages owned by the driver. This
325    avoids trying to migrate device private pages residing in other devices.
326    Currently only anonymous private VMA ranges can be migrated to or from
327    system memory and device private memory.
329    One of the first steps migrate_vma_setup() does is to invalidate other
332    walks to fill in the ``args->src`` array with PFNs to be migrated.
334    ``struct mmu_notifier_range`` with the ``event`` field set to
335    ``MMU_NOTIFY_MIGRATE`` and the ``migrate_pgmap_owner`` field set to
336    the ``args->pgmap_owner`` field passed to migrate_vma_setup(). This is
337    allows the device driver to skip the invalidation callback and only
342    entry results in a valid "zero" PFN stored in the ``args->src`` array.
343    This lets the driver allocate device private memory and clear it instead
344    of copying a page of zeros. Valid PTE entries to system memory or
346    from the LRU (if system memory since device private pages are not on
349    migrate_vma_setup() also clears the ``args->dst`` array.
351 3. The device driver allocates destination pages and copies source pages to
354    The driver checks each ``src`` entry to see if the ``MIGRATE_PFN_MIGRATE``
356    can also choose to skip migrating a page by not filling in the ``dst``
360    system memory page, locks the page with ``lock_page()``, and fills in the
366    invalidate device private MMU mappings and copy device private memory
367    to system memory or another device private page. The core Linux kernel
368    handles CPU page table invalidations so the device driver only has to
371    The driver can use ``migrate_pfn_to_page(src[i])`` to get the
372    ``struct page`` of the source and either copy the source page to the
373    destination or clear the destination device private memory if the pointer
374    is ``NULL`` meaning the source page was not populated in system memory.
388    information is now copied to destination ``struct page`` finalizing the
401    page's page table entry and releases the reference to the source and
408 Memory cgroup (memcg) and rss accounting
411 For now, device memory is accounted as any regular page in rss counters (either
413 file backed page, or shmem if device page is used for shared memory). This is a
414 deliberate choice to keep existing applications, that might start using device
415 memory without knowing about it, running unimpacted.
418 device memory and not a lot of regular system memory and thus not freeing much
419 system memory. We want to gather more real world experience on how applications
420 and system react under memory pressure in the presence of device memory before
421 deciding to account device memory differently.
424 Same decision was made for memory cgroup. Device memory pages are accounted
425 against same memory cgroup a regular page would be accounted to. This does
426 simplify migration to and from device memory. This also means that migration
427 back from device memory to regular memory cannot fail because it would
428 go above memory cgroup limit. We might revisit this choice latter on once we
429 get more experience in how device memory is used and its impact on memory
433 Note that device memory can never be pinned by a device driver nor through GUP
434 and thus such memory is always free upon process exit. Or when last reference
435 is dropped in case of shared memory or file backed memory.