networking/dsa/sja1105.rst

10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
17 These are SPI-managed automotive switches, with all ports being gigabit
21 set-and-forget use, with minimal dynamic interaction at runtime. They
56 Also the configuration is write-only (software cannot read it back from the
71 programmable filters for link-local destination MACs.
77 But by leveraging ``CONFIG_NET_DSA_TAG_8021Q`` (a software-defined DSA tagging
78 format based on VLANs), general-purpose traffic termination through the network
84 - Mode 1 (VLAN-unaware): a port is in this mode when it is used as a standalone
86 - Mode 2 (fully VLAN-aware): a port is in this mode when it is enslaved to a
88   the user through ``bridge vlan`` commands, but general-purpose (anything
92 - Mode 3 (best-effort VLAN-aware): a port is in this mode when enslaved to a
96   to 4094), so is the number of usable VIDs (maximum of 7 non-pvid VLANs per
103 +-------------+-----------+--------------+------------+
108 +-------------+-----------+--------------+------------+
112 +-------------+-----------+--------------+------------+
128   # Cannot use VLANs in range 1024-3071 while in Mode 3.
155 \* "maximum of 7 non-pvid VLANs per port": Decoding VLAN-tagged packets on the
157 switch to the CPU. In cross-chip topologies, the port that goes to the CPU
165 As an example, consider this cross-chip topology::
167   +-------------------------------------------------+
169   |           +-------------------------+           |
171   |           |   switch (non-sja1105)  |           |
172   |  +--------+-------------------------+--------+  |
175   |  |   +--------------+     +--------------+   |  |
178   +--+---+--------------+-----+--------------+---+--+
180   +-----------------------+ +-----------------------+
182   +-----+-----+-----+-----+ +-----+-----+-----+-----+
184   +-----+-----+-----+-----+ +-----+-----+-----+-----+
238 towards the CPU. It also consumes 1 retagging entry for each non-pvid VLAN that
245 - 8 retagging entries for VLANs 1 and 100 installed on its user ports
246   (``sw1p0`` - ``sw1p3``)
247 - 3 retagging entries for VLAN 100 installed on the user ports of SJA1105
248   switch 2 (``sw2p0`` - ``sw2p2``), because it also has ports that are
254 - 7 retagging entries for the bridge VLANs on its user ports (``sw2p0`` -
256 - 4 retagging entries for VLAN 100 installed on the user ports of SJA1105
257   switch 1 (``sw1p0`` - ``sw1p3``).
269 The hardware tags all traffic internally with a port-based VLAN (pvid), or it
285 ``vlan_filtering`` enslaves at least one switch port, the other un-bridged
299 The switch ports (swp0-3) are under br0.
301 with swp0-3.
313 Time-aware scheduling
314 ---------------------
317 specified in IEEE 802.1Q-2018 (formerly 802.1Qbv). This means it can be used to
318 ensure deterministic latency for priority traffic that is sent in-band with its
319 gate-open event in the network schedule.
321 This capability can be managed through the tc-taprio offload ('flags 2'). The
327 on the VLAN PCP bits (if no VLAN is present, the port-based default is used).
339 sub-interface on the DSA master port, and send normal (0x8100) VLAN-tagged
342 Management traffic (having DMAC 01-80-C2-xx-xx-xx or 01-19-1B-xx-xx-xx) is the
343 notable exception: the switch always treats it with a fixed priority and
354   set -e -u -o pipefail
369   if ! systemctl is-active --quiet ptp4l; then
375   # Phase-align the base time to the start of the next second.
376   sec=$(echo "${now}" | gawk -F. '{ print $1; }')
383           base-time ${base_time} \
384           sched-entry S $(gatemask 7) 100000 \
385           sched-entry S $(gatemask "0 1 2 3 4 5 6") 400000 \
388 It is possible to apply the tc-taprio offload on multiple egress ports. There
395 --------------------------------------
397 The switch is able to offload flow-based redirection of packets to a set of
399 making use of Virtual Links, a TTEthernet concept.
401 The driver supports 2 types of keys for Virtual Links:
403 - VLAN-aware virtual links: these match on destination MAC address, VLAN ID and
405 - VLAN-unaware virtual links: these match on destination MAC address only.
411 actions are requested, the driver creates a "non-critical" virtual link. When
412 the action list also contains tc-gate (more details below), the virtual link
413 becomes "time-critical" (draws frame buffers from a reserved memory partition,
433 Time-based ingress policing
434 ---------------------------
437 similarly to the Per-Stream Filtering and Policing (PSFP) clause specified in
438 IEEE 802.1Q-2018 (formerly 802.1Qci). This means it can be used to perform
439 tight timing-based admission control for up to 1024 flows (identified by a
443 This capability can be managed through the offload of the tc-gate action. As
444 routing actions are intrinsic to virtual links in TTEthernet (which performs
445 explicit routing of time-critical traffic and does not leave that in the hands
446 of the FDB, flooding etc), the tc-gate action may never appear alone when
450 Example: create a tc-taprio schedule that is phase-aligned with a tc-gate
461           sec=$(echo $now | awk -F. '{print $1}') && \
466           action gate base-time ${base_time} \
467           sched-entry OPEN  60000 -1 -1 \
468           sched-entry CLOSE 40000 -1 -1 \
474           sec=$(echo $now | awk -F. '{print $1}') && \
481           base-time ${base_time} \
482           sched-entry S 01  50000 \
483           sched-entry S 00  50000 \
487 one used for the tc-taprio offload. Therefore, the restrictions regarding the
488 fact that no two gate actions (either tc-gate or tc-taprio gates) may fire at
491 To come in handy, it is possible to share time-triggered virtual links across
500           base-time 0 \
501           sched-entry OPEN 50000000 -1 -1 \
502           sched-entry CLOSE 50000000 -1 -1 \
507 lack of destination ports and MTU enforcement checks). Byte-level counters are
516 RMII PHY role and out-of-band signaling
517 ---------------------------------------
524 On the other hand, the SJA1105 is only binary configurable - when in the RMII
528 In the RMII spec, the PHY can transmit extra out-of-band signals via RXD[1:0].
530 preamble of each frame. The MAC does not have this out-of-band signaling
533 clock signal, inevitably an RMII PHY-to-PHY connection is created. The SJA1105
536 simply encodes the extra symbols received from the SJA1105-as-PHY onto the
537 100Base-Tx wire.
542 The take-away is that in RMII mode, the SJA1105 must be let to drive the
545 RGMII fixed-link and internal delays
546 ------------------------------------
560 In the situation where the switch port is connected through an RGMII fixed-link
564 The take-away is that in RGMII mode, the switch's internal delays are only
567 the fixed-link are under control of the same Linux system).
568 As to why would a fixed-link interface ever change link speeds: there are
574 ---------------------------
576 The SJA1105 does not have an MDIO bus and does not perform in-band AN either.