Documentation/fpga/dfl.rst

2 FPGA Device Feature List (DFL) Framework Overview
11 The Device Feature List (DFL) FPGA framework (and drivers according to
19 Device Feature List (DFL) Overview
21 Device Feature List (DFL) defines a linked list of feature headers within the
31  +----------+  |   | Feature  |  |   | Feature  |  |   | Feature  |
37  +----------+  |   | Feature  |      | Feature  |      | Feature  |
65 Feature Header (Next_DFH) pointer.
67 Each FIU, AFU and Private Feature could implement its own functional registers.
69 e.g. FME Header Register Set, and the one for Private Feature, is named as
70 Feature Register Set, e.g. FME Partial Reconfiguration Feature Register Set.
72 This Device Feature List provides a way of linking features together, it's
73 convenient for software to locate each feature by walking through this list,
188                  | FPGA Container Device |    Device Feature List
201 (FPGA base region), discover feature devices and their private features from the
202 given Device Feature Lists and create platform devices for feature devices
205 feature device drivers.
223 	   bridges and FPGA regions during PR sub feature initialization. Once
234 After feature platform devices creation, matched platform drivers will be loaded
259 Feature Lists, as illustrated below:
362 Application needs to search each regionX folder, if feature device is found,
394 Performance reporting is one private feature implemented in FME. It could
475 many interrupts are supported for this private feature. Drivers also implement
488 new feature dev (FIU) following the same way as existing feature dev drivers
498 framework, as each private feature will be parsed automatically and related
500 Developer only needs to provide a sub feature driver with matched feature id.
501 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)