Documentation/driver-api/edac.rst

5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
20 provides the number of bits that the memory controller expects:
37 A memory controller channel, responsible to communicate with a group of
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
44 controller. Typically, it contains two channels. Two channels at the
52 * Single-channel
54 The data accessed by the memory controller is contained into one dimm
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
62 The data size accessed by the memory controller is interlaced into two
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
67 * Chip-select row
70 accessed. Common chip-select rows for single channel are 64 bits, for
71 dual channel 128 bits. It may not be visible by the memory controller,
73 it from the Memory Controller.
75 * Single-Ranked stick
77 A Single-ranked stick has 1 chip-select row of memory. Motherboards
78 commonly drive two chip-select pins to a memory stick. A single-ranked
83 * Double-Ranked stick
85 A double-ranked stick has two chip-select rows which access different
88 * Double-sided stick
90 **DEPRECATED TERM**, see :ref:`Double-Ranked stick <doubleranked>`.
92 A double-sided stick has two chip-select rows which access different sets
94 "Double-sided" is irrespective of the memory devices being mounted on
100 all of the memory sticks spanned by a chip-select row.  A single socket
101 set has two chip-select rows and if double-sided sticks are used these
102 will occupy those chip-select rows.
107 between chip-select rows and socket sets.
111 ------------------
113 Most of the EDAC core is focused on doing Memory Controller error detection.
118 .. kernel-doc:: include/linux/edac.h
120 .. kernel-doc:: drivers/edac/edac_mc.h
123 ---------------
129 .. kernel-doc:: drivers/edac/edac_pci.h
132 -----------
145 - CPU caches (L1 and L2)
146 - DMA engines
147 - Core CPU switches
148 - Fabric switch units
149 - PCIe interface controllers
150 - other EDAC/ECC type devices that can be monitored for
155 For example, a cache could be composed of L1, L2 and L3 levels of cache.
156 Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
160 	/sys/devices/system/edac/..
165 		/L1-cache/ce_count
167 		/L2-cache/ce_count
170 		/L1-cache/ce_count
172 		/L2-cache/ce_count
178 .. kernel-doc:: drivers/edac/edac_device.h