driver-api/dmaengine/provider.rst

21 will want to start a transfer, it will assert a DMA request (DRQ) by
25 parameter: the transfer size. At each clock cycle, it would transfer a
26 byte of data from one buffer to another, until the transfer size has
31 cycle. For example, we may want to transfer as much data as the
36 parameter called the transfer width.
44 transfer into smaller sub-transfers.
59 transfer, and whenever the transfer is started, the controller will go
73 transfer width and the transfer size.
118   should contain a bitmask of the supported source transfer width
121   should contain a bitmask of the supported destination transfer width
128   granularity of the transfer residue reported to dma_set_residue.
188   - The device is able to trigger a dummy transfer that will
216   - If you want to transfer a single contiguous memory buffer,
223   - A cyclic transfer is a transfer where the chunk collection will
231   - The device supports interleaved transfer.
233   - These transfers can transfer data from a non-contiguous buffer
235     transfer data from a non-contiguous data set to a continuous
239     want to transfer a portion of uncompressed data directly to the
260   - The device supports repeated transfers. A repeated transfer, indicated by
261     the DMA_PREP_REPEAT transfer flag, is similar to a cyclic transfer in that
267     the current needs of DMA clients, support for additional transfer types
272   - The device supports replacing repeated transfers at end of transfer (EOT)
273     by queuing a new transfer with the DMA_PREP_LOAD_EOT flag set.
275   - Support for replacing a currently running transfer at another point (such
276     as end of burst instead of end of transfer) will be added in the future
283 after each transfer. In case of a ring buffer, they may loop
290 associated with a transaction. The DMA controller role is to transfer the
315     On transfer completion the DMA driver must copy the metadata to the client
317     After the transfer completion, DMA drivers must not touch the metadata
373     for the transfer being prepared, and should create a hardware
383     during the transfer setup at probe time to avoid putting to
388     particular transfer.
411     - result: This provides the transfer result defined by
414     - residue: Provides the residue bytes of the transfer for those that
420     and starts the transfer. Whenever that transfer is done, it
436   - In the case of a cyclic transfer, it should only take into
466   - Pauses a transfer on the channel
473   - Resumes a transfer on the channel
489     wait until the currently active transfer has completely stopped.
515 - Should be called at the end of an async TX transfer, and can be
551   because the DMA'd data wasn't used, it can resubmit the transfer right after
576   - If set, the transfer will be automatically repeated when it ends until a
577     new transfer is queued on the same channel with the DMA_PREP_LOAD_EOT flag.
578     If the next transfer to be queued on the channel does not have the
579     DMA_PREP_LOAD_EOT flag set, the current transfer will be repeated until the
587   - If set, the transfer will replace the transfer currently being executed at
588     the end of the transfer.
595     repeating the last repeated transfer and ignore the new transfers being
597     stuck on the previous transfer.
606 that handles the end of transfer interrupts in the handler, but defer
607 most work to a tasklet, including the start of a new transfer whenever
608 the previous transfer ended.
610 This is a rather inefficient design though, because the inter-transfer
613 in between, which will slow down the global transfer rate.
616 transfer in your tasklet, move that part to the interrupt handler in
628 - Transfer: A collection of chunks (be it contiguous or not)