bindings/spi/spi-sifive.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive SPI controller
10   - Pragnesh Patel <pragnesh.patel@sifive.com>
11   - Paul Walmsley  <paul.walmsley@sifive.com>
12   - Palmer Dabbelt <palmer@sifive.com>
15   - $ref: "spi-controller.yaml#"
20       - const: sifive,fu540-c000-spi
21       - const: sifive,spi0
24       Should be "sifive,<chip>-spi" and "sifive,spi<version>".
25       Supported compatible strings are -
26       "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
27       onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
28       SPI v0 IP block with no chip integration tweaks.
29       Please refer to sifive-blocks-ip-versioning.txt for details
31       SPI RTL that corresponds to the IP block version numbers can be found here -
32       https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
37       - description: SPI registers region
38       - description: Memory mapped flash region
49   sifive,fifo-depth:
56   sifive,max-bits-per-word:
64   - compatible
65   - reg
66   - interrupts
67   - clocks
72   - |
74       compatible = "sifive,fu540-c000-spi", "sifive,spi0";
76       interrupt-parent = <&plic>;
79       #address-cells = <1>;
80       #size-cells = <0>;
81       sifive,fifo-depth = <8>;
82       sifive,max-bits-per-word = <8>;