bindings/spi/qcom%2Cspi-qcom-qspi.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11   - Mukesh Savaliya <msavaliy@codeaurora.org>
12   - Akash Asthana <akashast@codeaurora.org>
14 description: The QSPI controller allows SPI protocol communication in single,
19   - $ref: /spi/spi-controller.yaml#
24       - const: qcom,sdm845-qspi
25       - const: qcom,qspi-v1
33   clock-names:
35       - const: iface
36       - const: core
40       - description: AHB clock
41       - description: QSPI core clock
47   interconnect-names:
49       - const: qspi-config
50       - const: qspi-memory
53   - compatible
54   - reg
55   - interrupts
56   - clock-names
57   - clocks
62   - |
63     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
64     #include <dt-bindings/interrupt-controller/arm-gic.h>
67         #address-cells = <2>;
68         #size-cells = <2>;
70         qspi: spi@88df000 {
71             compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
73             #address-cells = <1>;
74             #size-cells = <0>;
76             clock-names = "iface", "core";
81                 compatible = "jedec,spi-nor";
83                 spi-max-frequency = <25000000>;
84                 spi-tx-bus-width = <2>;
85                 spi-rx-bus-width = <2>;