Lines Matching full:description

13 description:
37       - description: Address and length of PHY's common serdes block.
67     description:
71     description:
75     description:
82     description:
113             - description: Phy aux clock.
114             - description: Phy config clock.
115             - description: 19.2 MHz ref clk.
116             - description: Phy common block aux clock.
125             - description: reset of phy block.
126             - description: phy common block reset.
141             - description: Phy aux clock.
142             - description: Phy config clock.
143             - description: 19.2 MHz ref clk.
151             - description: reset of phy block.
152             - description: phy common block reset.
153             - description: phy's ahb cfg block reset.
172             - description: Phy aux clock.
173             - description: Phy config clock.
174             - description: 19.2 MHz ref clk.
182             - description: reset of phy block.
183             - description: phy common block reset.
198             - description: 19.2 MHz ref clk.
204             - description: PHY reset in the UFS controller.
221             - description: 19.2 MHz ref clk.
222             - description: Phy reference aux clock.
229             - description: PHY reset in the UFS controller.
243             - description: pipe clk.
249             - description: reset of phy block.
250             - description: phy common block reset.
266             - description: Phy aux clock.
267             - description: Phy config clock.
268             - description: 19.2 MHz ref clk.
269             - description: Phy refgen clk.
278             - description: reset of phy block.