bindings/pci/xilinx-versal-cpm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CPM Host Controller device tree for Xilinx Versal SoCs
10   - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
13   - $ref: /schemas/pci/pci-bus.yaml#
17     const: xlnx,versal-cpm-host-1.00
21       - description: Configuration space region and bridge registers.
22       - description: CPM system level control and status registers.
24   reg-names:
26       - const: cfg
27       - const: cpm_slcr
30     maxItems: 1
32   msi-map:
39   "#interrupt-cells":
40     const: 1
42   interrupt-controller:
46       "#address-cells":
48       "#interrupt-cells":
49         const: 1
50       "interrupt-controller": true
54   - reg
55   - reg-names
56   - "#interrupt-cells"
57   - interrupts
58   - interrupt-parent
59   - interrupt-map
60   - interrupt-map-mask
61   - bus-range
62   - msi-map
63   - interrupt-controller
68   - |
70     versal {
71                #address-cells = <2>;
72                #size-cells = <2>;
74                        compatible = "xlnx,versal-cpm-host-1.00";
76                        #address-cells = <3>;
77                        #interrupt-cells = <1>;
78                        #size-cells = <2>;
80                        interrupt-parent = <&gic>;
81                        interrupt-map-mask = <0 0 0 7>;
82                        interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
83                                        <0 0 0 2 &pcie_intc_0 1>,
86                        bus-range = <0x00 0xff>;
89                        msi-map = <0x0 &its_gic 0x0 0x10000>;
92                        reg-names = "cfg", "cpm_slcr";
93                        pcie_intc_0: interrupt-controller {
94                                #address-cells = <0>;
95                                #interrupt-cells = <1>;
96                                interrupt-controller;