bindings/net/ethernet-phy.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Generic Binding
10   - Andrew Lunn <andrew@lunn.ch>
11   - Florian Fainelli <f.fainelli@gmail.com>
12   - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
16 # case, the node name is the one we want to match on, while the
17 # compatible is optional.
21       pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24     - $nodename
28     pattern: "^ethernet-phy(@[a-f0-9]+)?$"
32       - const: ethernet-phy-ieee802.3-c22
34       - const: ethernet-phy-ieee802.3-c45
36       - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
38           If the PHY reports an incorrect ID (or none at all) then the
39           compatible list may contain an entry with the correct PHY ID
41           The first group of digits is the 16 bit Phy Identifier 1
42           register, this is the chip vendor OUI bits 3:18. The
43           second group of digits is the Phy Identifier 2 register,
44           this is the chip vendor OUI bits 19:24, followed by 10
46       - items:
47           - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
48           - const: ethernet-phy-ieee802.3-c22
49       - items:
50           - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
51           - const: ethernet-phy-ieee802.3-c45
57       The ID number for the PHY.
62   max-speed:
64       - 10
65       - 100
66       - 1000
67       - 2500
68       - 5000
69       - 10000
70       - 20000
71       - 25000
72       - 40000
73       - 50000
74       - 56000
75       - 100000
76       - 200000
78       Maximum PHY supported speed in Mbits / seconds.
80   broken-turn-around:
83       If set, indicates the PHY device does not correctly release
87   enet-phy-lane-swap:
90       If set, indicates the PHY will swap the TX/RX lanes to
94   eee-broken-100tx:
100   eee-broken-1000t:
106   eee-broken-10gt:
112   eee-broken-1000kx:
118   eee-broken-10gkx4:
124   eee-broken-10gkr:
130   phy-is-integrated:
133       If set, indicates that the PHY is integrated into the same
135       should be configured to ensure the integrated PHY is
137       should be configured so that the external PHY is used.
142   reset-names:
143     const: phy
145   reset-gpios:
148       The GPIO phandle and specifier for the PHY reset signal.
150   reset-assert-us:
153       property is missing the delay will be skipped.
155   reset-deassert-us:
158       this property is missing the delay will be skipped.
165   rx-internal-delay-ps:
167       RGMII Receive PHY Clock Delay defined in pico seconds.  This is used for
168       PHY's that have configurable RX internal delays.  If this property is
169       present then the PHY applies the RX delay.
171   tx-internal-delay-ps:
173       RGMII Transmit PHY Clock Delay defined in pico seconds.  This is used for
174       PHY's that have configurable TX internal delays. If this property is
175       present then the PHY applies the TX delay.
178   - reg
183   - |
185         #address-cells = <1>;
186         #size-cells = <0>;
188         ethernet-phy@0 {
189             compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45";
190             interrupt-parent = <&PIC>;
195             reset-names = "phy";
196             reset-gpios = <&gpio1 4 1>;
197             reset-assert-us = <1000>;
198             reset-deassert-us = <2000>;