bindings/mtd/nand-controller.yaml

4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
14   The NAND controller should be represented with its own DT node, and
15   all NAND chips attached to this controller should be defined as
16   children nodes of the NAND controller. This representation should be
31     pattern: "^nand-controller(@.*)?"
42   "^nand@[a-f0-9]$":
49       nand-ecc-mode:
52           embedded in the NAND controller) or software correction
54           and should be replaced by soft and nand-ecc-algo.
58       nand-ecc-engine:
64           1/ The ECC engine is part of the NAND controller, in this
66           2/ The ECC engine is part of the NAND part (on-die), in this
71       nand-use-soft-ecc-engine:
75       nand-no-ecc-engine:
79       nand-ecc-placement:
89       nand-ecc-algo:
95       nand-bus-width:
97           Bus width to the NAND chip
102       nand-on-flash-bbt:
113       nand-ecc-strength:
119       nand-ecc-step-size:
125       nand-ecc-maximize:
134           want to make your NAND as reliable as possible.
136       nand-is-boot-medium:
139           Whether or not the NAND chip is a boot medium. Drivers might
143       nand-rb:
152           Ready/Busy pins. Active state refers to the NAND ready state and
166     nand-controller {
172       nand@0 {
174         nand-ecc-mode = "soft";
175         nand-ecc-algo = "bch";