bindings/mmc/sdhci-am654.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI AM654 MMC Controller
11   - Ulf Hansson <ulf.hansson@linaro.org>
14   - $ref: mmc-controller.yaml#
19       - ti,am654-sdhci-5.1
20       - ti,j721e-sdhci-8bit
21       - ti,j721e-sdhci-4bit
22       - ti,j7200-sdhci-8bit
23       - ti,j721e-sdhci-4bit
31   power-domains:
37     description: Handles to input clocks
39   clock-names:
43       - const: clk_ahb
44       - const: clk_xin
46   # PHY output tap delays:
47   # Used to delay the data valid window and align it to the sampling clock.
51   ti,otap-del-sel-legacy:
52     description: Output tap delay for SD/MMC legacy timing
57   ti,otap-del-sel-mmc-hs:
58     description: Output tap delay for MMC high speed timing
63   ti,otap-del-sel-sd-hs:
64     description: Output tap delay for SD high speed timing
69   ti,otap-del-sel-sdr12:
70     description: Output tap delay for SD UHS SDR12 timing
75   ti,otap-del-sel-sdr25:
76     description: Output tap delay for SD UHS SDR25 timing
81   ti,otap-del-sel-sdr50:
82     description: Output tap delay for SD UHS SDR50 timing
87   ti,otap-del-sel-sdr104:
88     description: Output tap delay for SD UHS SDR104 timing
93   ti,otap-del-sel-ddr50:
94     description: Output tap delay for SD UHS DDR50 timing
99   ti,otap-del-sel-ddr52:
100     description: Output tap delay for eMMC DDR52 timing
105   ti,otap-del-sel-hs200:
106     description: Output tap delay for eMMC HS200 timing
111   ti,otap-del-sel-hs400:
112     description: Output tap delay for eMMC HS400 timing
117   # PHY input tap delays:
118   # Used to delay the data valid window and align it to the sampling clock for
121   ti,itap-del-sel-legacy:
122     description: Input tap delay for SD/MMC legacy timing
127   ti,itap-del-sel-mmc-hs:
128     description: Input tap delay for MMC high speed timing
133   ti,itap-del-sel-sd-hs:
134     description: Input tap delay for SD high speed timing
139   ti,itap-del-sel-sdr12:
140     description: Input tap delay for SD UHS SDR12 timing
145   ti,itap-del-sel-sdr25:
146     description: Input tap delay for SD UHS SDR25 timing
151   ti,itap-del-sel-ddr52:
152     description: Input tap delay for MMC DDR52 timing
157   ti,trm-icp:
163   ti,driver-strength-ohm:
167       - 33
168       - 40
169       - 50
170       - 66
171       - 100
173   ti,strobe-sel:
174     description: strobe select delay for HS400 speed mode.
177   ti,clkbuf-sel:
178     description: Clock Delay Buffer Select
182   - compatible
183   - reg
184   - interrupts
185   - clocks
186   - clock-names
187   - ti,otap-del-sel-legacy
192   - |
193     #include <dt-bindings/interrupt-controller/irq.h>
194     #include <dt-bindings/interrupt-controller/arm-gic.h>
197         #address-cells = <2>;
198         #size-cells = <2>;
200         mmc0: mmc@4f80000 {
201             compatible = "ti,am654-sdhci-5.1";
203             power-domains = <&k3_pds 47>;
205             clock-names = "clk_ahb", "clk_xin";
207             sdhci-caps-mask = <0x80000007 0x0>;
208             mmc-ddr-1_8v;
209             ti,otap-del-sel-legacy = <0x0>;
210             ti,otap-del-sel-mmc-hs = <0x0>;
211             ti,otap-del-sel-ddr52 = <0x5>;
212             ti,otap-del-sel-hs200 = <0x5>;
213             ti,otap-del-sel-hs400 = <0x0>;
214             ti,itap-del-sel-legacy = <0x10>;
215             ti,itap-del-sel-mmc-hs = <0xa>;
216             ti,itap-del-sel-ddr52 = <0x3>;
217             ti,trm-icp = <0x8>;