bindings/mmc/cdns%2Csdhci.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Masahiro Yamada <yamada.masahiro@socionext.com>
11   - Piotr Sroka <piotrs@cadence.com>
14   - $ref: mmc-controller.yaml
19       - enum:
20           - socionext,uniphier-sd4hc
21       - const: cdns,sd4hc
37   cdns,phy-input-delay-sd-highspeed:
38     description: Value of the delay in the input path for SD high-speed timing
41     maximum: 0x1f
43   cdns,phy-input-delay-legacy:
47     maximum: 0x1f
49   cdns,phy-input-delay-sd-uhs-sdr12:
53     maximum: 0x1f
55   cdns,phy-input-delay-sd-uhs-sdr25:
59     maximum: 0x1f
61   cdns,phy-input-delay-sd-uhs-sdr50:
65     maximum: 0x1f
67   cdns,phy-input-delay-sd-uhs-ddr50:
71     maximum: 0x1f
73   cdns,phy-input-delay-mmc-highspeed:
74     description: Value of the delay in the input path for MMC high-speed timing
77     maximum: 0x1f
79   cdns,phy-input-delay-mmc-ddr:
80     description: Value of the delay in the input path for eMMC high-speed DDR timing
88     maximum: 0x1f
90   cdns,phy-dll-delay-sdclk:
96     maximum: 0x7f
98   cdns,phy-dll-delay-sdclk-hsmmc:
101       HS400_ES speed modes.
104     maximum: 0x7f
106   cdns,phy-dll-delay-strobe:
109       HS400 / HS400_ES speed modes.
112     maximum: 0x7f
115   - compatible
116   - reg
117   - interrupts
118   - clocks
123   - |
125         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
129         bus-width = <8>;
130         mmc-ddr-1_8v;
131         mmc-hs200-1_8v;
132         mmc-hs400-1_8v;
133         cdns,phy-dll-delay-sdclk = <0>;