bindings/memory-controllers/st%2Cstm32-fmc2-ebi.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
11   asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14     - to translate AXI transactions into the appropriate external device
16     - to meet the access time requirements of the external devices
17   All external devices share the addresses, data and control signals with the
18   controller. Each external device is accessed by means of a unique Chip
19   Select. The FMC2 performs only one access at a time to an external device.
22   - Christophe Kerello <christophe.kerello@st.com>
26     const: st,stm32mp1-fmc2-ebi
37   "#address-cells":
40   "#size-cells":
45       Reflects the memory layout with four integer values per bank. Format:
46       <bank-number> 0 <address of the bank> <size>
49   "^.*@[0-4],[a-f0-9]+$":
56       st,fmc2-ebi-cs-transaction-type:
75       st,fmc2-ebi-cs-cclk-enable:
82       st,fmc2-ebi-cs-mux-enable:
88       st,fmc2-ebi-cs-buswidth:
94       st,fmc2-ebi-cs-waitpol-high:
99       st,fmc2-ebi-cs-waitcfg-enable:
106       st,fmc2-ebi-cs-wait-enable:
112       st,fmc2-ebi-cs-asyncwait-enable:
118       st,fmc2-ebi-cs-cpsize:
119         description: CRAM page size. The controller splits the burst access
120           when the memory page is reached. By default, no burst split when
126       st,fmc2-ebi-cs-byte-lane-setup-ns:
130       st,fmc2-ebi-cs-address-setup-ns:
134       st,fmc2-ebi-cs-address-hold-ns:
139       st,fmc2-ebi-cs-data-setup-ns:
143       st,fmc2-ebi-cs-bus-turnaround-ns:
147       st,fmc2-ebi-cs-data-hold-ns:
151       st,fmc2-ebi-cs-clk-period-ns:
155       st,fmc2-ebi-cs-data-latency-ns:
159       st,fmc2_ebi-cs-write-address-setup-ns:
163       st,fmc2-ebi-cs-write-address-hold-ns:
168       st,fmc2-ebi-cs-write-data-setup-ns:
172       st,fmc2-ebi-cs-write-bus-turnaround-ns:
176       st,fmc2-ebi-cs-write-data-hold-ns:
180       st,fmc2-ebi-cs-max-low-pulse-ns:
183           reaches 0, the controller splits the current access, toggles NE to
187       - reg
190   - "#address-cells"
191   - "#size-cells"
192   - compatible
193   - reg
194   - clocks
195   - ranges
200   - |
201     #include <dt-bindings/interrupt-controller/arm-gic.h>
202     #include <dt-bindings/clock/stm32mp1-clks.h>
203     #include <dt-bindings/reset/stm32mp1-resets.h>
204     memory-controller@58002000 {
205       #address-cells = <2>;
206       #size-cells = <1>;
207       compatible = "st,stm32mp1-fmc2-ebi";
219         compatible = "mtd-ram";
221         bank-width = <2>;
223         st,fmc2-ebi-cs-transaction-type = <1>;
224         st,fmc2-ebi-cs-address-setup-ns = <60>;
225         st,fmc2-ebi-cs-data-setup-ns = <30>;
226         st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
229       nand-controller@4,0 {
230         #address-cells = <1>;
231         #size-cells = <0>;
232         compatible = "st,stm32mp1-fmc2-nfc";
243         dma-names = "tx", "rx", "ecc";
247           nand-on-flash-bbt;
248           #address-cells = <1>;
249           #size-cells = <1>;