bindings/memory-controllers/nvidia%2Ctegra20-emc.txt

4 - name : Should be emc
5 - #address-cells : Should be 1
6 - #size-cells : Should be 0
7 - compatible : Should contain "nvidia,tegra20-emc".
8 - reg : Offset and length of the register set for the device
9 - nvidia,use-ram-code : If present, the sub-nodes will be addressed
12   irrespective of ram-code configuration.
13 - interrupts : Should contain EMC General interrupt.
14 - clocks : Should contain EMC clock.
20 	memory-controller@7000f400 {
21 		#address-cells = < 1 >;
22 		#size-cells = < 0 >;
23 		compatible = "nvidia,tegra20-emc";
30 Embedded Memory Controller ram-code table
32 If the emc node has the nvidia,use-ram-code property present, then the
34 apply for which ram-code settings.
36 If the emc node lacks the nvidia,use-ram-code property, this level is omitted
41 - name : Should be emc-tables
42 - nvidia,ram-code : the binary representation of the ram-code board strappings
64   on a 2-pin "ram code" bootstrap setting on the board. The values of
69 - name : Should be emc-table
70 - compatible : Should contain "nvidia,tegra20-emc-table".
71 - reg : either an opaque enumerator to tell different tables apart, or
73 - clock-frequency : the clock frequency for the EMC at which this
75 - nvidia,emc-registers : a 46 word array of EMC registers to be programmed
76   for operation at the 'clock-frequency' setting.
86 		emc-table@166000 {
88 			compatible = "nvidia,tegra20-emc-table";
89 			clock-frequency = < 166000 >;
90 			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
96 		emc-table@333000 {
98 			compatible = "nvidia,tegra20-emc-table";
99 			clock-frequency = < 333000 >;
100 			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0