Lines Matching +full:a +full:- +full:child +full:- +full:node +full:- +full:property
5 using a queued mailbox interrupt mechanism. The IP block is external to the
7 communication is achieved through a set of registers for message storage and
10 Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
12 within a processor subsystem, and there can be more than one line going to a
15 (excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
16 programmable through a set of interrupt configuration registers, and have a rx
22 All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
25 routed to different processor sub-systems on DRA7xx as they are routed through
26 the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E
27 SoCs has each of these instances form a cluster and combine multiple clusters
28 into a single IP block present within the Main NavSS. The interrupt lines from
30 over a limited number of common interrupt output lines of an Interrupt Router.
32 Mailbox Device Node:
34 A Mailbox device node is used to represent a Mailbox IP instance/cluster within
35 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
38 --------------------
39 - compatible: Should be one of the following,
40 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
41 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
42 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
44 "ti,am654-mailbox" for K3 AM65x and J721E SoCs
45 - reg: Contains the mailbox register address range (base
47 - interrupts: Contains the interrupt information for the mailbox
50 - #mbox-cells: Common mailbox binding property to identify the number
53 - ti,mbox-num-users: Number of targets (processor devices) that the mailbox
55 - ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
57 SoC-specific Required properties:
58 ---------------------------------
61 - ti,hwmods: Name of the hwmod associated with the mailbox. This
62 should be defined in the mailbox node only if the node
63 is not defined as a child node of a corresponding sysc
64 interconnect node.
67 - interrupt-parent: Should contain a phandle to the TI-SCI interrupt
68 controller node that is used to dynamically program
72 Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
74 Child Nodes:
76 A child node is used for representing the actual sub-mailbox device that is
77 used for the communication between the host processor and a remote processor.
78 Each child node should have a unique node name across all the different
82 --------------------
83 - ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo
84 - ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo
86 Sub-mailbox Descriptor Data
87 ---------------------------
88 Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of
90 Cell #1 (fifo_id) - mailbox fifo id used either for transmitting
91 (ti,mbox-tx) or for receiving (ti,mbox-rx)
92 Cell #2 (irq_id) - irq identifier index number to use from the parent's
93 interrupts data. Should be 0 for most of the cases, a
96 Cell #3 (usr_id) - mailbox user id for identifying the interrupt line
97 associated with generating a tx/rx fifo interrupt.
100 --------------------
101 - ti,mbox-send-noirq: Quirk flag to allow the client user of this sub-mailbox
102 to send messages without triggering a Tx ready interrupt,
104 sub-mailboxes used to communicate with WkupM3 remote
109 A device needing to communicate with a target processor device should specify
111 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
112 for details). Each value of the mboxes property should contain a phandle to the
113 mailbox controller device node and an args specifier that will be the phandle to
114 the intended sub-mailbox child node to be used for communication. The equivalent
115 "mbox-names" property value can be used to give a name to the communication channel
120 --------
124 compatible = "ti,omap4-mailbox";
128 #mbox-cells = <1>;
129 ti,mbox-num-users = <3>;
130 ti,mbox-num-fifos = <8>;
132 ti,mbox-tx = <0 0 0>;
133 ti,mbox-rx = <1 0 0>;
136 ti,mbox-tx = <3 0 0>;
137 ti,mbox-rx = <2 0 0>;
149 compatible = "ti,omap4-mailbox";
153 #mbox-cells = <1>;
154 ti,mbox-num-users = <4>;
155 ti,mbox-num-fifos = <8>;
157 ti,mbox-tx = <0 0 0>;
158 ti,mbox-rx = <0 0 3>;
166 compatible = "ti,am654-mailbox";
168 #mbox-cells = <1>;
169 ti,mbox-num-users = <4>;
170 ti,mbox-num-fifos = <16>;
171 interrupt-parent = <&intr_main_navss>;
174 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
175 ti,mbox-tx = <1 0 0>;
176 ti,mbox-rx = <0 0 0>;