Lines Matching full:interrupts

15   which are then mapped to 10 possible output interrupts through two levels
18   interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
23   differences on the output interrupts 2 through 9. If this property is not
24   defined, it implies that all the PRUSS INTC output interrupts 2 through 9
29   different possible output interrupts. The additional output interrupts (10
51   interrupts:
55       All the interrupts generated towards the main host processor in the SoC.
76       host_event (target) [cell 3] as the value of the interrupts property in
78       interrupts through 2 levels of many-to-one mapping i.e. events to channel
79       mapping and channels to host interrupts so through this property entire
85       Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC
86       output interrupts 2 through 9) that are not connected to the Arm interrupt
88       SoC. Define this property when any of 8 interrupts should not be handled
93               "host_intr7" interrupts connected to MPU, and other ICSSG
99   - interrupts
119             interrupts = <20 21 22 23 24 25 26 27>;
145             interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,