bindings/interrupt-controller/sifive%2Cplic-1.0.0.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11   SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
12   (PLIC) high-level specification in the RISC-V Privileged Architecture
13   specification. The PLIC connects all external interrupts in the system to all
14   hart contexts in the system, via the external interrupt source in each hart.
17   in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
20   Each interrupt can be enabled on per-context basis. Any context can claim
28   While the PLIC supports both edge-triggered and level-triggered interrupts,
30   specified in the PLIC device-tree binding.
32   While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
33   "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
34   contains a specific memory layout, which is documented in chapter 8 of the
35   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
38   - Sagar Kadam <sagar.kadam@sifive.com>
39   - Paul Walmsley  <paul.walmsley@sifive.com>
40   - Palmer Dabbelt <palmer@dabbelt.com>
45       - const: sifive,fu540-c000-plic
46       - const: sifive,plic-1.0.0
51   '#address-cells':
54   '#interrupt-cells':
57   interrupt-controller: true
59   interrupts-extended:
62       Specifies which contexts are connected to the PLIC, with "-1" specifying
64       riscv,cpu-intc node, which has a riscv node as parent.
69       Specifies how many external interrupts are supported by this controller.
72   - compatible
73   - '#address-cells'
74   - '#interrupt-cells'
75   - interrupt-controller
76   - reg
77   - interrupts-extended
78   - riscv,ndev
83   - |
84     plic: interrupt-controller@c000000 {
85       #address-cells = <0>;
86       #interrupt-cells = <1>;
87       compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
88       interrupt-controller;
89       interrupts-extended = <