bindings/interrupt-controller/arm%2Cgic.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Marc Zyngier <marc.zyngier@arm.com>
14   interrupts (PPI), shared processor interrupts (SPI) and software
22   - $ref: /schemas/interrupt-controller.yaml#
27       - items:
28           - enum:
29               - arm,arm11mp-gic
30               - arm,cortex-a15-gic
31               - arm,cortex-a7-gic
32               - arm,cortex-a5-gic
33               - arm,cortex-a9-gic
34               - arm,eb11mp-gic
35               - arm,gic-400
36               - arm,pl390
37               - arm,tc11mp-gic
38               - nvidia,tegra210-agic
39               - qcom,msm-8660-qgic
40               - qcom,msm-qgic2
42       - items:
43           - const: arm,gic-400
44           - enum:
45               - arm,cortex-a15-gic
46               - arm,cortex-a7-gic
48       - items:
49           - const: arm,arm1176jzf-devchip-gic
50           - const: arm,arm11mp-gic
52       - items:
53           - const: brcm,brahma-b15-gic
54           - const: arm,cortex-a15-gic
56   interrupt-controller: true
58   "#address-cells":
60   "#size-cells":
63   "#interrupt-cells":
66       The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
70       SPI interrupts are in the range [0-987].  PPI interrupts are in the
71       range [0-15].
75           1 = low-to-high edge triggered
76           2 = high-to-low edge triggered (invalid for SPIs)
77           4 = active high level-sensitive
78           8 = active low level-sensitive (invalid for SPIs).
89       Specifies base physical address(s) and size of the GIC registers. The
90       first region is the GIC distributor register base and size. The 2nd region
91       is the GIC cpu interface register base and size.
94       required for specifying the base physical address and size of the VGIC
96       control register base and size. The 2nd additional region is the GIC
97       virtual cpu interface register base and size.
109   cpu-offset:
110     description: per-cpu offset within the distributor and cpu interface
112       is cpu-offset * cpu-nr.
119   clock-names:
123       - const: ic_clk # for "arm,arm11mp-gic"
124       - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
125       - items: # for "arm,cortex-a9-gic"
126           - const: PERIPHCLK
127           - const: PERIPHCLKEN
128       - const: clk # for "arm,gic-400" and "nvidia,tegra210"
129       - const: gclk #for "arm,pl390"
131   power-domains:
138   - compatible
139   - reg
142   "^v2m@[0-9a-f]+$":
145       * GICv2m extension for MSI/MSI-x support (Optional)
147       Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
148       This is enabled by specifying v2m sub-node(s).
152         const: arm,gic-v2m-frame
154       msi-controller: true
158         description: GICv2m MSI interface register base and size
160       arm,msi-base-spi:
162           this property should contain the SPI base of the MSI frame, overriding
166       arm,msi-num-spis:
173       - compatible
174       - msi-controller
175       - reg
182   - |
184     intc: interrupt-controller@fff11000 {
185       compatible = "arm,cortex-a9-gic";
186       #interrupt-cells = <3>;
187       #address-cells = <1>;
188       interrupt-controller;
193   - |
195     interrupt-controller@2c001000 {
196       compatible = "arm,cortex-a15-gic";
197       #interrupt-cells = <3>;
198       interrupt-controller;
206   - |
207     // GICv2m extension for MSI/MSI-x support
208     interrupt-controller@e1101000 {
209       compatible = "arm,gic-400";
210       #interrupt-cells = <3>;
211       #address-cells = <1>;
212       #size-cells = <1>;
213       interrupt-controller;
222         compatible = "arm,gic-v2m-frame";
223         msi-controller;
230         compatible = "arm,gic-v2m-frame";
231         msi-controller;