Lines Matching +full:interrupt +full:- +full:affinity
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <marc.zyngier@arm.com>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
30 interrupt-controller: true
32 "#address-cells":
34 "#size-cells":
39 "#interrupt-cells":
41 Specifies the number of cells needed to encode an interrupt source.
43 If the system requires describing PPI affinity, then the value must
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
50 The 2nd cell contains the interrupt number for the interrupt type.
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extented SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
61 interrupt is affine to. The interrupt must be a PPI, and the node
62 pointed must be a subnode of the "ppi-partitions" subnode. For
63 interrupt types other than PPI or PPIs that are not partitionned,
64 this cell must be zero. See the "ppi-partitions" node description
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
87 Interrupt source of the VGIC maintenance interrupt.
90 redistributor-stride:
98 "#redistributor-regions":
105 msi-controller:
107 Only present if the Message Based Interrupt functionnality is
108 being exposed by the HW, and the mbi-ranges property present.
110 mbi-ranges:
115 $ref: /schemas/types.yaml#/definitions/uint32-matrix
120 mbi-alias:
125 $ref: /schemas/types.yaml#/definitions/uint32-array
130 ppi-partitions:
133 PPI affinity can be expressed as a single "ppi-partitions" node,
134 containing a set of sub-nodes.
136 "^interrupt-partition-[0-9]+$":
139 affinity:
140 $ref: /schemas/types.yaml#/definitions/phandle-array
146 - affinity
149 mbi-ranges: [ msi-controller ]
150 msi-controller: [ mbi-ranges ]
153 - compatible
154 - interrupts
155 - reg
158 "^gic-its@": false
159 "^interrupt-controller@[0-9a-f]+$": false
160 # msi-controller is preferred, but allow other names
161 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
164 GICv3 has one or more Interrupt Translation Services (ITS) that are
168 const: arm,gic-v3-its
170 msi-controller: true
172 "#msi-cells":
174 The single msi-cell is the DeviceID of the device which will generate
183 socionext,synquacer-pre-its:
186 address and size of the pre-ITS window.
187 $ref: /schemas/types.yaml#/definitions/uint32-array
193 - compatible
194 - msi-controller
195 - "#msi-cells"
196 - reg
203 - |
204 gic: interrupt-controller@2cf00000 {
205 compatible = "arm,gic-v3";
206 #interrupt-cells = <3>;
207 #address-cells = <1>;
208 #size-cells = <1>;
210 interrupt-controller;
218 msi-controller;
219 mbi-ranges = <256 128>;
221 msi-controller@2c200000 {
222 compatible = "arm,gic-v3-its";
223 msi-controller;
224 #msi-cells = <1>;
229 interrupt-controller@2c010000 {
230 compatible = "arm,gic-v3";
231 #interrupt-cells = <4>;
232 #address-cells = <1>;
233 #size-cells = <1>;
235 interrupt-controller;
236 redistributor-stride = <0x0 0x40000>; // 256kB stride
237 #redistributor-regions = <2>;
239 <0x2d000000 0x800000>, // GICR 1: CPUs 0-31
240 <0x2e000000 0x800000>, // GICR 2: CPUs 32-63
246 msi-controller@2c200000 {
247 compatible = "arm,gic-v3-its";
248 msi-controller;
249 #msi-cells = <1>;
253 msi-controller@2c400000 {
254 compatible = "arm,gic-v3-its";
255 msi-controller;
256 #msi-cells = <1>;
260 ppi-partitions {
261 part0: interrupt-partition-0 {
262 affinity = <&cpu0 &cpu2>;
265 part1: interrupt-partition-1 {
266 affinity = <&cpu1 &cpu3>;