bindings/dma/st%2Cstm32-dma.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA Controller bindings
10   The STM32 DMA is a general-purpose direct memory access controller capable of
11   supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12   DMA clients connected to the STM32 DMA controller must use the format
13   described in the dma.txt file, using a four-cell specifier for each
14   channel: a phandle to the DMA controller plus the following four integer cells:
17     3. A 32bit mask specifying the DMA channel configuration which are device
19         -bit 9: Peripheral Increment Address
22         -bit 10: Memory Increment Address
25         -bit 15: Peripheral Increment Offset Size
27           0x1: offset size is fixed to 4 (32-bit alignment)
28         -bit 16-17: Priority level
33     4. A 32bit bitfield value specifying DMA features which are device dependent:
34        -bit 0-1: DMA FIFO threshold selection
39        -bit 2: DMA direct mode
40          0x0: FIFO mode with threshold selectable with bit 0-1
41          0x1: Direct mode: each DMA request immediately initiates a transfer
46   - Amelie Delaunay <amelie.delaunay@st.com>
49   - $ref: "dma-controller.yaml#"
52   "#dma-cells":
56     const: st,stm32-dma
66     description: Should contain all of the per-channel DMA
68       DMA channel index.
75     description: if defined, it indicates that the controller
76       supports memory-to-memory transfer
79   - compatible
80   - reg
81   - clocks
82   - interrupts
87   - |
88     #include <dt-bindings/interrupt-controller/arm-gic.h>
89     #include <dt-bindings/clock/stm32mp1-clks.h>
90     #include <dt-bindings/reset/stm32mp1-resets.h>
91     dma-controller@40026400 {
92       compatible = "st,stm32-dma";
103       #dma-cells = <4>;
106       dma-requests = <8>;