display/mediatek/mediatek%2Chdmi.txt

8 - compatible: Should be "mediatek,<chip>-hdmi".
9 - the supported chips are mt2701, mt7623 and mt8173
10 - reg: Physical base address and length of the controller's registers
11 - interrupts: The interrupt signal from the function block.
12 - clocks: device clocks
13   See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
14 - clock-names: must contain "pixel", "pll", "bclk", and "spdif".
15 - phys: phandle link to the HDMI PHY node.
16   See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
17 - phy-names: must contain "hdmi"
18 - mediatek,syscon-hdmi: phandle link and register offset to the system
21 - ports: A node containing input and output port nodes with endpoint
23 - port@0: The input port in the ports node should be connected to a DPI output
25 - port@1: The output port in the ports node should be connected to the input
26   port of a connector node that contains a ddc-i2c-bus property, or to the
35 - compatible: Should be "mediatek,<chip>-cec"
36 - the supported chips are mt7623 and mt8173
37 - reg: Physical base address and length of the controller's registers
38 - interrupts: The interrupt signal from the function block.
39 - clocks: device clock
41 HDMI DDC
44 The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
45 The Mediatek's I2C controller is used to interface with I2C devices.
48 - compatible: Should be "mediatek,<chip>-hdmi-ddc"
49 - the supported chips are mt7623 and mt8173
50 - reg: Physical base address and length of the controller's registers
51 - clocks: device clock
52 - clock-names: Should be "ddc-i2c".
57 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
61 - compatible: "mediatek,<chip>-hdmi-phy"
62 - the supported chips are mt2701, mt7623 and mt8173
63 - reg: Physical base address and length of the module's registers
64 - clocks: PLL reference clock
65 - clock-names: must contain "pll_ref"
66 - clock-output-names: must be "hdmitx_dig_cts" on mt8173
67 - #phy-cells: must be <0>
68 - #clock-cells: must be <0>
71 - mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
72 - mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
77 	compatible = "mediatek,mt8173-cec";
83 hdmi_phy: hdmi-phy@10209100 {
84 	compatible = "mediatek,mt8173-hdmi-phy";
87 	clock-names = "pll_ref";
88 	clock-output-names = "hdmitx_dig_cts";
91 	#clock-cells = <0>;
92 	#phy-cells = <0>;
95 hdmi_ddc0: i2c@11012000 {
96 	compatible = "mediatek,mt8173-hdmi-ddc";
100 	clock-names = "ddc-i2c";
104 	compatible = "mediatek,mt8173-hdmi";
111 	clock-names = "pixel", "pll", "bclk", "spdif";
112 	pinctrl-names = "default";
113 	pinctrl-0 = <&hdmi_pin>;
115 	phy-names = "hdmi";
116 	mediatek,syscon-hdmi = <&mmsys 0x900>;
117 	assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
118 	assigned-clock-parents = <&hdmi_phy>;
121 		#address-cells = <1>;
122 		#size-cells = <0>;
128 				remote-endpoint = <&dpi0_out>;
136 				remote-endpoint = <&hdmi_con_in>;
143 	compatible = "hdmi-connector";
145 	ddc-i2c-bus = <&hdmiddc0>;
149 			remote-endpoint = <&hdmi0_out>;