Documentation/core-api/dma-attributes.rst

5 This document describes the semantics of the DMA attributes that are
11 DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
12 may be weakly ordered, that is that reads and writes may pass each other.
15 those that do not will simply ignore the attribute and exhibit default
21 DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
25 those that do not will simply ignore the attribute and exhibit default
37 that you won't dereference the pointer returned by dma_alloc_attr(). You
38 can treat it as a cookie that must be passed to dma_mmap_attrs() and
39 dma_free_attrs(). Make sure that both of these also get this attribute
43 DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the
57 (usually it means that the cache has been flushed or invalidated
64 the CPU cache for the given buffer assuming that it has been already
82 This is a hint to the DMA-mapping subsystem that it's probably not worth
83 the time to try to allocate memory to in a way that gives better TLB
87 - You know that the accesses to this memory won't thrash the TLB.
88   You might know that the accesses are likely to be sequential or
89   that they aren't sequential but it's unlikely you'll ping-pong
90   between many addresses that are likely to be in different physical
92 - You know that the penalty of TLB misses while accessing the
96 - You know that the DMA mapping is fairly transitory.  If you expect
101 Setting this hint doesn't guarantee that you won't get huge pages, but it
102 means that we won't try quite as hard to get them.
116 and can actually flood the system logs with error messages that aren't any
130 subsystem that the buffer is fully accessible at the elevated privilege