Lines Matching full:will

28 Therefore when software page table changes occur, the kernel will
35 any previous page table modification whatsoever will be
46 'mm' will be visible to the cpu. That is, after running,
47 there will be no entries in the TLB for 'mm'.
60 'start' to 'end-1' will be visible to the cpu. That is, after
61 running, there will be no entries in the TLB for 'mm' for
85 user virtual address 'addr' will be visible to the cpu. That
86 is, after running, there will be no entries in the TLB for
106 the sequence will be in one of the following forms::
120 The cache level flush will always be first, because this allows
140 the caches. That is, after running, there will be no cache
149 the caches. That is, after running, there will be no cache
162 addresses from the cache. After running, there will be no
190 After running, there will be no entries in the cache for
199 highmem. It will be called right before all of the kmaps
202 After running, there will be no entries in the cache for
213 there will be no entries in the cache for the kernel address
233 size). This setting will force the SYSv IPC layer to only allow user
266 user will ultimately have this page mapped, and the 'page'
296 sure that kernel reads of these pages will see the most recent
304 for pagecache pages, it will clear this bit when such
334 of arbitrary user pages (f.e. for ptrace()) it will use
340 likely that you will need to flush the instruction cache
369 When the kernel stores into addresses that it will execute
372 If the icache does not snoop stores then this routine will need