Documentation/bpf/bpf_design_QA.rst

18 Q: Is BPF a generic instruction set similar to x64 and arm64?
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34 with two most used architectures x64 and arm64 (and takes into
45 A: NO. BPF calling convention only allows registers R1-R5 to be used
47 (unlike x64 ISA that allows msft, cdecl and other conventions)
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62 Q: Does C-calling convention diminishes possible use cases?
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79 bpf-to-bpf calls, indirect calls, loops, global variables,
80 jump tables, read-only sections, and all other normal constructs
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96 program analysis. Currently, that limit is set to 1 million.
98 of 1 million NOP instructions. There is a limit to the maximum number
99 of subsequent branches, a limit to the number of nested bpf-to-bpf
103 There are also non-numerical limits that can cause the program
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129 Q: BPF instructions mapping not one-to-one to native CPU
131 Q: It seems not all BPF instructions are one-to-one to native CPU.
132 For example why BPF_JNE and other compare and jumps are not cpu-like?
137 Q: Why BPF_DIV instruction doesn't map to x64 div?
139 A: Because if we picked one-to-one relationship to x64 it would have made
141 needs div-by-zero runtime check.
165 New instructions that don't have one-to-one mapping to HW instructions
168 Q: BPF 32-bit subregister requirements
170 Q: BPF 32-bit subregisters have a requirement to zero upper 32-bits of BPF
171 registers which makes BPF inefficient virtual machine for 32-bit
172 CPU architectures and 32-bit HW accelerators. Can true 32-bit registers
177 But some optimizations on zero-ing the upper 32 bits for BPF registers are
179 programs for 32-bit architectures.
182 on 32-bit subregisters, provided the option -mattr=+alu32 is passed for
184 instructions for which zero-ing the upper bits of the destination register
185 is required, and insert an explicit zero-extension (zext) instruction
187 support, the JIT back-ends do not need to clear the upper bits for
189 back-ends simply need to support code generation for that mov32 variant,
193 Note that it is possible for a JIT back-end to have partial hardware
197 back-end: if one instruction has hardware support for zext and if the next
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241 A: Sort-of.
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