Documentation/arm64/booting.rst

13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
14 counterpart.  EL2 is the hypervisor level and exists only in non-secure
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
82   u64 res2	= 0;		/* reserved */
83   u64 res3	= 0;		/* reserved */
84   u64 res4	= 0;		/* reserved */
86   u32 res5;			/* reserved (used for PE COFF offset) */
91 - As of v3.17, all fields are little endian unless stated otherwise.
93 - code0/code1 are responsible for branching to stext.
95 - when booting through EFI, code0/code1 are initially skipped.
100 - Prior to v3.17, the endianness of text_offset was not specified.  In
102   endianness of the kernel.  Where image_size is non-zero image_size is
103   little-endian and must be respected.  Where image_size is zero,
106 - The flags field (introduced in v3.17) is a little-endian 64-bit field
111   Bit 1-2	Kernel Page size.
113 			* 0 - Unspecified.
114 			* 1 - 4K
115 			* 2 - 16K
116 			* 3 - 64K
121 			  to the base of DRAM, since memory below it is not
125 			  memory
126   Bits 4-63	Reserved.
129 - When image_size is zero, a bootloader should attempt to keep as much
130   memory as possible free for use by the kernel immediately after the
140 NOTE: versions prior to v4.6 cannot make use of memory below the
145 entirely within a 1 GB aligned physical memory window of up to 32 GB in
148 Any memory described to the kernel (even that below the start of the
149 image) which is not marked as reserved from the kernel (e.g., with a
155 - Quiesce all DMA capable devices so that memory does not get
159 - Primary CPU general-purpose register settings:
161     - x0 = physical address of device tree blob (dtb) in system RAM.
162     - x1 = 0 (reserved for future use)
163     - x2 = 0 (reserved for future use)
164     - x3 = 0 (reserved for future use)
166 - CPU mode
171   the virtualisation extensions) or non-secure EL1.
173 - Caches, MMUs
189 - Architected timers
196 - Coherency
203 - System registers
209   - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
211   - The value of SCR_EL3.FIQ must be the same as the one present at boot
215   - If EL3 is present:
217       - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
218       - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
219       - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
223   - If the kernel is entered at EL1:
225       - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
226       - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
228   - The DT or ACPI tables must describe a GICv3 interrupt controller.
233   - If EL3 is present:
237   - If the kernel is entered at EL1:
241   - The DT or ACPI tables must describe a GICv2 interrupt controller.
245   - If EL3 is present:
247     - SCR_EL3.APK (bit 16) must be initialised to 0b1
248     - SCR_EL3.API (bit 17) must be initialised to 0b1
250   - If the kernel is entered at EL1:
252     - HCR_EL2.APK (bit 40) must be initialised to 0b1
253     - HCR_EL2.API (bit 41) must be initialised to 0b1
257   - If EL3 is present:
259     - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
260     - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
261     - AMCNTENSET0_EL0 must be initialised to 0b1111
262     - AMCNTENSET1_EL0 must be initialised to a platform specific value
266   - If the kernel is entered at EL1:
268     - AMCNTENSET0_EL0 must be initialised to 0b1111
269     - AMCNTENSET1_EL0 must be initialised to a platform specific value
280 - The primary CPU must jump directly to the first instruction of the
282   an 'enable-method' property for each cpu node.  The supported
283   enable-methods are described below.
288 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
290   naturally-aligned 64-bit zero-initalised memory location.
292   These CPUs should spin outside of the kernel in a reserved area of
293   memory (communicated to the kernel by a /memreserve/ region in the
294   device tree) polling their cpu-release-addr location, which must be
295   contained in the reserved region.  A wfe instruction may be inserted
296   to reduce the overhead of the busy-loop and a sev will be issued by
298   cpu-release-addr returns a non-zero value, the CPU must jump to this
299   value.  The value will be written as a single 64-bit little-endian
303 - CPUs with a "psci" enable method should remain outside of
304   the kernel (i.e. outside of the regions of memory described to the
305   kernel in the memory node, or in a reserved area of memory described
314 - Secondary CPU general-purpose register settings
316   - x0 = 0 (reserved for future use)
317   - x1 = 0 (reserved for future use)
318   - x2 = 0 (reserved for future use)
319   - x3 = 0 (reserved for future use)