Documentation/arm64/booting.rst

10 is relevant to all public releases of the AArch64 Linux kernel.
13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
14 counterpart.  EL2 is the hypervisor level and exists only in non-secure
15 mode. EL3 is the highest priority level and exists only in secure mode.
19 is passed to the Linux kernel.  This may include secure monitor and
28 3. Decompress the kernel image
29 4. Call the kernel image
33 ---------------------------
38 kernel will use for volatile data storage in the system.  It performs
39 this in a machine dependent manner.  (It may use internal algorithms
41 the RAM in the machine, or any other method the boot loader designer
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
51 not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
52 using blocks of up to 2 megabytes in size, it must not be placed within
56 the 512 MB region starting at text_offset bytes below the kernel Image.
58 3. Decompress the kernel image
59 ------------------------------
63 The AArch64 kernel does not currently provide a decompressor and
70 4. Call the kernel image
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
81   u64 flags;			/* kernel flags, little endian */
91 - As of v3.17, all fields are little endian unless stated otherwise.
93 - code0/code1 are responsible for branching to stext.
95 - when booting through EFI, code0/code1 are initially skipped.
100 - Prior to v3.17, the endianness of text_offset was not specified.  In
101   these cases image_size is zero and text_offset is 0x80000 in the
102   endianness of the kernel.  Where image_size is non-zero image_size is
103   little-endian and must be respected.  Where image_size is zero,
106 - The flags field (introduced in v3.17) is a little-endian 64-bit field
110   Bit 0		Kernel endianness.  1 if BE, 0 if LE.
111   Bit 1-2	Kernel Page size.
113 			* 0 - Unspecified.
114 			* 1 - 4K
115 			* 2 - 16K
116 			* 3 - 64K
117   Bit 3		Kernel physical placement
124 			  2MB aligned base may be anywhere in physical
126   Bits 4-63	Reserved.
129 - When image_size is zero, a bootloader should attempt to keep as much
130   memory as possible free for use by the kernel immediately after the
131   end of the kernel image. The amount of space required will vary
135 address anywhere in usable system RAM and called there. The region
137 special significance to the kernel, and may be used for other purposes.
139 use by the kernel.
144 If an initrd/initramfs is passed to the kernel at boot, it must reside
145 entirely within a 1 GB aligned physical memory window of up to 32 GB in
146 size that fully covers the kernel Image as well.
148 Any memory described to the kernel (even that below the start of the
149 image) which is not marked as reserved from the kernel (e.g., with a
150 memreserve region in the device tree) will be considered as available to
151 the kernel.
153 Before jumping into the kernel, the following conditions must be met:
155 - Quiesce all DMA capable devices so that memory does not get
159 - Primary CPU general-purpose register settings:
161     - x0 = physical address of device tree blob (dtb) in system RAM.
162     - x1 = 0 (reserved for future use)
163     - x2 = 0 (reserved for future use)
164     - x3 = 0 (reserved for future use)
166 - CPU mode
168   All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
170   The CPU must be in either EL2 (RECOMMENDED in order to have access to
171   the virtualisation extensions) or non-secure EL1.
173 - Caches, MMUs
178   entries corresponding to the loaded kernel image.
180   The address range corresponding to the loaded kernel image must be
181   cleaned to the PoC. In the presence of a system cache or other
189 - Architected timers
193   kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
196 - Coherency
198   All CPUs to be booted by the kernel must be part of the same coherency
199   domain on entry to the kernel.  This may require IMPLEMENTATION DEFINED
203 - System registers
206   the kernel image will be entered must be initialised by software at a
207   higher exception level to prevent execution in an UNKNOWN state.
209   - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
211   - The value of SCR_EL3.FIQ must be the same as the one present at boot
212     time whenever the kernel is executing.
214   For systems with a GICv3 interrupt controller to be used in v3 mode:
215   - If EL3 is present:
217       - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
218       - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
219       - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
220         all CPUs the kernel is executing on, and must stay constant
221         for the lifetime of the kernel.
223   - If the kernel is entered at EL1:
225       - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
226       - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
228   - The DT or ACPI tables must describe a GICv3 interrupt controller.
230   For systems with a GICv3 interrupt controller to be used in
233   - If EL3 is present:
237   - If the kernel is entered at EL1:
241   - The DT or ACPI tables must describe a GICv2 interrupt controller.
245   - If EL3 is present:
247     - SCR_EL3.APK (bit 16) must be initialised to 0b1
248     - SCR_EL3.API (bit 17) must be initialised to 0b1
250   - If the kernel is entered at EL1:
252     - HCR_EL2.APK (bit 40) must be initialised to 0b1
253     - HCR_EL2.API (bit 41) must be initialised to 0b1
257   - If EL3 is present:
259     - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
260     - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
261     - AMCNTENSET0_EL0 must be initialised to 0b1111
262     - AMCNTENSET1_EL0 must be initialised to a platform specific value
266   - If the kernel is entered at EL1:
268     - AMCNTENSET0_EL0 must be initialised to 0b1111
269     - AMCNTENSET1_EL0 must be initialised to a platform specific value
275 enter the kernel in the same exception level.
277 The boot loader is expected to enter the kernel on each CPU in the
280 - The primary CPU must jump directly to the first instruction of the
281   kernel image.  The device tree blob passed by this CPU must contain
282   an 'enable-method' property for each cpu node.  The supported
283   enable-methods are described below.
286   properties and insert them into the blob prior to kernel entry.
288 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
289   property in their cpu node.  This property identifies a
290   naturally-aligned 64-bit zero-initalised memory location.
292   These CPUs should spin outside of the kernel in a reserved area of
293   memory (communicated to the kernel by a /memreserve/ region in the
294   device tree) polling their cpu-release-addr location, which must be
295   contained in the reserved region.  A wfe instruction may be inserted
296   to reduce the overhead of the busy-loop and a sev will be issued by
298   cpu-release-addr returns a non-zero value, the CPU must jump to this
299   value.  The value will be written as a single 64-bit little-endian
303 - CPUs with a "psci" enable method should remain outside of
304   the kernel (i.e. outside of the regions of memory described to the
305   kernel in the memory node, or in a reserved area of memory described
306   to the kernel by a /memreserve/ region in the device tree).  The
307   kernel will issue CPU_ON calls as described in ARM document number ARM
309   processors") to bring CPUs into the kernel.
311   The device tree should contain a 'psci' node, as described in
314 - Secondary CPU general-purpose register settings
316   - x0 = 0 (reserved for future use)
317   - x1 = 0 (reserved for future use)
318   - x2 = 0 (reserved for future use)
319   - x3 = 0 (reserved for future use)