admin-guide/mm/numaperf.rst

9 as CPU cache coherence, but may have different performance. For example,
20  +------------------+     +------------------+
21  | Compute Node 0   +-----+ Compute Node 1   |
23  +--------+---------+     +--------+---------+
25  +--------+---------+     +--------+---------+
27  +------------------+     +--------+---------+
35 performance when accessing a given memory target. Each initiator-target
47 	# symlinks -v /sys/devices/system/node/nodeX/access0/targets/
48 	relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
50 	# symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
51 	relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
82 	# tree -P "read*|write*" /sys/devices/system/node/nodeY/access0/initiators/
84 	|-- read_bandwidth
85 	|-- read_latency
86 	|-- write_bandwidth
87 	`-- write_latency
100 NUMA Cache
107 by the last memory level in the hierarchy. The system meanwhile uses
108 higher performing memory to transparently cache access to progressively
111 The term "far memory" is used to denote the last level memory in the
112 hierarchy. Each increasing cache level provides higher performing
114 cache provided by the system.
116 This numbering is different than CPU caches where the cache level (ex:
117 L1, L2, L3) uses the CPU-side view where each increased level is lower
118 performing. In contrast, the memory cache level is centric to the last
119 level memory, so the higher numbered cache level corresponds to  memory
122 The memory-side caches are not directly addressable by software. When
124 near memory cache if it is present. If it is not present, the system
125 accesses the next level of memory until there is either a hit in that
126 cache level, or it reaches far memory.
129 to use the system. Software may optionally query the memory cache
135 When the kernel first registers a memory cache with a node, the kernel
141 a memory-side cache, or that information is not accessible to the kernel.
143 The attributes for each level of cache is provided under its cache
144 level index::
150 Each cache level's directory provides its attributes. For example, the
151 following shows a single cache level and the attributes available for
156 	|-- index1
157 	|   |-- indexing
158 	|   |-- line_size
159 	|   |-- size
160 	|   `-- write_policy
162 The "indexing" will be 0 if it is a direct-mapped cache, and non-zero
163 for any other indexed based, multi-way associativity.
165 The "line_size" is the number of bytes accessed from the next cache
166 level on a miss.
168 The "size" is the number of bytes provided by this cache level.
170 The "write_policy" will be 0 for write-back, and non-zero for
171 write-through caching.
178 - Section 5.2.27