admin-guide/mm/numaperf.rst

9 as CPU cache coherence, but may have different performance. For example,
14 characteristics.  Some memory may share the same node as a CPU, and others
20  +------------------+     +------------------+
21  | Compute Node 0   +-----+ Compute Node 1   |
23  +--------+---------+     +--------+---------+
25  +--------+---------+     +--------+---------+
27  +------------------+     +--------+---------+
35 performance when accessing a given memory target. Each initiator-target
47 	# symlinks -v /sys/devices/system/node/nodeX/access0/targets/
48 	relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
50 	# symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
51 	relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
82 	# tree -P "read*|write*" /sys/devices/system/node/nodeY/access0/initiators/
84 	|-- read_bandwidth
85 	|-- read_latency
86 	|-- write_bandwidth
87 	`-- write_latency
96 Access class 1 takes the same form but only includes values for CPU to
116 This numbering is different than CPU caches where the cache level (ex:
117 L1, L2, L3) uses the CPU-side view where each increased level is lower
118 performing. In contrast, the memory cache level is centric to the last
120 nearer to the CPU, and further from far memory.
122 The memory-side caches are not directly addressable by software. When
141 a memory-side cache, or that information is not accessible to the kernel.
156 	|-- index1
157 	|   |-- indexing
158 	|   |-- line_size
159 	|   |-- size
160 	|   `-- write_policy
162 The "indexing" will be 0 if it is a direct-mapped cache, and non-zero
163 for any other indexed based, multi-way associativity.
170 The "write_policy" will be 0 for write-back, and non-zero for
171 write-through caching.
178 - Section 5.2.27