admin-guide/hw-vuln/tsx_async_abort.rst

1 .. SPDX-License-Identifier: GPL-2.0
3 TAA - TSX Asynchronous Abort
11 -------------------
14 Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8)
15 is 0 in the IA32_ARCH_CAPABILITIES MSR.  On processors where the MDS_NO bit
16 (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations
23 ------------
28    CVE-2019-11135  TAA    TSX Asynchronous Abort (TAA) condition on some
36 -------
43 hardware transactional memory support to improve performance of multi-threaded
58 Because the buffers are potentially shared between Hyper-Threads cross
59 Hyper-Thread attacks are possible.
70 ----------------
87 -----------------------
96 .. list-table::
98    * - 'Vulnerable'
99 …- The CPU is affected by this vulnerability and the microcode and kernel mitigation are not applie…
100    * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
101      - The system tries to clear the buffers but the microcode might not support the operation.
102    * - 'Mitigation: Clear CPU buffers'
103      - The microcode has been updated to clear the buffers. TSX is still enabled.
104    * - 'Mitigation: TSX disabled'
105      - TSX is disabled.
106    * - 'Not affected'
107      - The CPU is not affected by this issue.
114 If the processor is vulnerable, but the availability of the microcode-based
129 --------------------
153 ---------------------------------------------
163   full	        TAA mitigation is enabled. If TSX is enabled, on an affected
165                 systems which are MDS-affected and deploy MDS mitigation,
169   full,nosmt    The same as tsx_async_abort=full, with SMT disabled on
172                 CPU is not vulnerable to cross-thread TAA attacks.
175 Not specifying this option is equivalent to "tsx_async_abort=full". For
200                 several previous speculation-related CVEs, and so there may be
213   tsx=on     tsx_async_abort=full         The system will use VERW to clear CPU
214                                           buffers. Cross-thread attacks are still
216   tsx=on     tsx_async_abort=full,nosmt   As above, cross-thread attacks on SMT
219   tsx=off    tsx_async_abort=full         TSX might be disabled if microcode
222   tsx=off    tsx_async_abort=full,nosmt   Ditto
227 For unaffected platforms "tsx=on" and "tsx_async_abort=full" does not clear CPU
232 combinations of CPUID bit MD_CLEAR and IA32_ARCH_CAPABILITIES MSR bits MDS_NO
248 --------------------------
273 -------------------
277   - Deploy TSX disable mitigation (tsx_async_abort=full tsx=off).