Lines Matching +full:gpio +full:- +full:mux +full:- +full:clock
2 * wm8904.c -- WM8904 ALSA SoC Audio driver
85 /* DC servo configuration - cached offset values */
90 0x8904, /* R0 - SW Reset and ID */
91 0x0000, /* R1 - Revision */
94 0x0018, /* R4 - Bias Control 0 */
95 0x0000, /* R5 - VMID Control 0 */
96 0x0000, /* R6 - Mic Bias Control 0 */
97 0x0000, /* R7 - Mic Bias Control 1 */
98 0x0001, /* R8 - Analogue DAC 0 */
99 0x9696, /* R9 - mic Filter Control */
100 0x0001, /* R10 - Analogue ADC 0 */
102 0x0000, /* R12 - Power Management 0 */
104 0x0000, /* R14 - Power Management 2 */
105 0x0000, /* R15 - Power Management 3 */
108 0x0000, /* R18 - Power Management 6 */
110 0x945E, /* R20 - Clock Rates 0 */
111 0x0C05, /* R21 - Clock Rates 1 */
112 0x0006, /* R22 - Clock Rates 2 */
114 0x0050, /* R24 - Audio Interface 0 */
115 0x000A, /* R25 - Audio Interface 1 */
116 0x00E4, /* R26 - Audio Interface 2 */
117 0x0040, /* R27 - Audio Interface 3 */
120 0x00C0, /* R30 - DAC Digital Volume Left */
121 0x00C0, /* R31 - DAC Digital Volume Right */
122 0x0000, /* R32 - DAC Digital 0 */
123 0x0008, /* R33 - DAC Digital 1 */
126 0x00C0, /* R36 - ADC Digital Volume Left */
127 0x00C0, /* R37 - ADC Digital Volume Right */
128 0x0010, /* R38 - ADC Digital 0 */
129 0x0000, /* R39 - Digital Microphone 0 */
130 0x01AF, /* R40 - DRC 0 */
131 0x3248, /* R41 - DRC 1 */
132 0x0000, /* R42 - DRC 2 */
133 0x0000, /* R43 - DRC 3 */
134 0x0085, /* R44 - Analogue Left Input 0 */
135 0x0085, /* R45 - Analogue Right Input 0 */
136 0x0044, /* R46 - Analogue Left Input 1 */
137 0x0044, /* R47 - Analogue Right Input 1 */
147 0x002D, /* R57 - Analogue OUT1 Left */
148 0x002D, /* R58 - Analogue OUT1 Right */
149 0x0039, /* R59 - Analogue OUT2 Left */
150 0x0039, /* R60 - Analogue OUT2 Right */
151 0x0000, /* R61 - Analogue OUT12 ZC */
157 0x0000, /* R67 - DC Servo 0 */
158 0x0000, /* R68 - DC Servo 1 */
159 0xAAAA, /* R69 - DC Servo 2 */
161 0xAAAA, /* R71 - DC Servo 4 */
162 0xAAAA, /* R72 - DC Servo 5 */
163 0x0000, /* R73 - DC Servo 6 */
164 0x0000, /* R74 - DC Servo 7 */
165 0x0000, /* R75 - DC Servo 8 */
166 0x0000, /* R76 - DC Servo 9 */
167 0x0000, /* R77 - DC Servo Readback 0 */
180 0x0000, /* R90 - Analogue HP 0 */
184 0x0000, /* R94 - Analogue Lineout 0 */
188 0x0000, /* R98 - Charge Pump 0 */
194 0x0004, /* R104 - Class W 0 */
198 0x0000, /* R108 - Write Sequencer 0 */
199 0x0000, /* R109 - Write Sequencer 1 */
200 0x0000, /* R110 - Write Sequencer 2 */
201 0x0000, /* R111 - Write Sequencer 3 */
202 0x0000, /* R112 - Write Sequencer 4 */
206 0x0000, /* R116 - FLL Control 1 */
207 0x0007, /* R117 - FLL Control 2 */
208 0x0000, /* R118 - FLL Control 3 */
209 0x2EE0, /* R119 - FLL Control 4 */
210 0x0004, /* R120 - FLL Control 5 */
211 0x0014, /* R121 - GPIO Control 1 */
212 0x0010, /* R122 - GPIO Control 2 */
213 0x0010, /* R123 - GPIO Control 3 */
214 0x0000, /* R124 - GPIO Control 4 */
216 0x0000, /* R126 - Digital Pulls */
217 0x0000, /* R127 - Interrupt Status */
218 0xFFFF, /* R128 - Interrupt Status Mask */
219 0x0000, /* R129 - Interrupt Polarity */
220 0x0000, /* R130 - Interrupt Debounce */
224 0x0000, /* R134 - EQ1 */
225 0x000C, /* R135 - EQ2 */
226 0x000C, /* R136 - EQ3 */
227 0x000C, /* R137 - EQ4 */
228 0x000C, /* R138 - EQ5 */
229 0x000C, /* R139 - EQ6 */
230 0x0FCA, /* R140 - EQ7 */
231 0x0400, /* R141 - EQ8 */
232 0x00D8, /* R142 - EQ9 */
233 0x1EB5, /* R143 - EQ10 */
234 0xF145, /* R144 - EQ11 */
235 0x0B75, /* R145 - EQ12 */
236 0x01C5, /* R146 - EQ13 */
237 0x1C58, /* R147 - EQ14 */
238 0xF373, /* R148 - EQ15 */
239 0x0A54, /* R149 - EQ16 */
240 0x0558, /* R150 - EQ17 */
241 0x168E, /* R151 - EQ18 */
242 0xF829, /* R152 - EQ19 */
243 0x07AD, /* R153 - EQ20 */
244 0x1103, /* R154 - EQ21 */
245 0x0564, /* R155 - EQ22 */
246 0x0559, /* R156 - EQ23 */
247 0x4000, /* R157 - EQ24 */
251 0x0000, /* R161 - Control Interface Test 1 */
294 0x0000, /* R204 - Analogue Output Bias 0 */
337 0x0000, /* R247 - FLL NCO Test 0 */
338 0x0019, /* R248 - FLL NCO Test 1 */
346 { 0xFFFF, 0xFFFF, 1 }, /* R0 - SW Reset and ID */
347 { 0x0000, 0x0000, 0 }, /* R1 - Revision */
350 { 0x001F, 0x001F, 0 }, /* R4 - Bias Control 0 */
351 { 0x0047, 0x0047, 0 }, /* R5 - VMID Control 0 */
352 { 0x007F, 0x007F, 0 }, /* R6 - Mic Bias Control 0 */
353 { 0xC007, 0xC007, 0 }, /* R7 - Mic Bias Control 1 */
354 { 0x001E, 0x001E, 0 }, /* R8 - Analogue DAC 0 */
355 { 0xFFFF, 0xFFFF, 0 }, /* R9 - mic Filter Control */
356 { 0x0001, 0x0001, 0 }, /* R10 - Analogue ADC 0 */
358 { 0x0003, 0x0003, 0 }, /* R12 - Power Management 0 */
360 { 0x0003, 0x0003, 0 }, /* R14 - Power Management 2 */
361 { 0x0003, 0x0003, 0 }, /* R15 - Power Management 3 */
364 { 0x000F, 0x000F, 0 }, /* R18 - Power Management 6 */
366 { 0x7001, 0x7001, 0 }, /* R20 - Clock Rates 0 */
367 { 0x3C07, 0x3C07, 0 }, /* R21 - Clock Rates 1 */
368 { 0xD00F, 0xD00F, 0 }, /* R22 - Clock Rates 2 */
370 { 0x1FFF, 0x1FFF, 0 }, /* R24 - Audio Interface 0 */
371 { 0x3DDF, 0x3DDF, 0 }, /* R25 - Audio Interface 1 */
372 { 0x0F1F, 0x0F1F, 0 }, /* R26 - Audio Interface 2 */
373 { 0x0FFF, 0x0FFF, 0 }, /* R27 - Audio Interface 3 */
376 { 0x00FF, 0x01FF, 0 }, /* R30 - DAC Digital Volume Left */
377 { 0x00FF, 0x01FF, 0 }, /* R31 - DAC Digital Volume Right */
378 { 0x0FFF, 0x0FFF, 0 }, /* R32 - DAC Digital 0 */
379 { 0x1E4E, 0x1E4E, 0 }, /* R33 - DAC Digital 1 */
382 { 0x00FF, 0x01FF, 0 }, /* R36 - ADC Digital Volume Left */
383 { 0x00FF, 0x01FF, 0 }, /* R37 - ADC Digital Volume Right */
384 { 0x0073, 0x0073, 0 }, /* R38 - ADC Digital 0 */
385 { 0x1800, 0x1800, 0 }, /* R39 - Digital Microphone 0 */
386 { 0xDFEF, 0xDFEF, 0 }, /* R40 - DRC 0 */
387 { 0xFFFF, 0xFFFF, 0 }, /* R41 - DRC 1 */
388 { 0x003F, 0x003F, 0 }, /* R42 - DRC 2 */
389 { 0x07FF, 0x07FF, 0 }, /* R43 - DRC 3 */
390 { 0x009F, 0x009F, 0 }, /* R44 - Analogue Left Input 0 */
391 { 0x009F, 0x009F, 0 }, /* R45 - Analogue Right Input 0 */
392 { 0x007F, 0x007F, 0 }, /* R46 - Analogue Left Input 1 */
393 { 0x007F, 0x007F, 0 }, /* R47 - Analogue Right Input 1 */
403 { 0x017F, 0x01FF, 0 }, /* R57 - Analogue OUT1 Left */
404 { 0x017F, 0x01FF, 0 }, /* R58 - Analogue OUT1 Right */
405 { 0x017F, 0x01FF, 0 }, /* R59 - Analogue OUT2 Left */
406 { 0x017F, 0x01FF, 0 }, /* R60 - Analogue OUT2 Right */
407 { 0x000F, 0x000F, 0 }, /* R61 - Analogue OUT12 ZC */
413 { 0x000F, 0x000F, 0 }, /* R67 - DC Servo 0 */
414 { 0xFFFF, 0xFFFF, 1 }, /* R68 - DC Servo 1 */
415 { 0x0F0F, 0x0F0F, 0 }, /* R69 - DC Servo 2 */
417 { 0x007F, 0x007F, 0 }, /* R71 - DC Servo 4 */
418 { 0x007F, 0x007F, 0 }, /* R72 - DC Servo 5 */
419 { 0x00FF, 0x00FF, 1 }, /* R73 - DC Servo 6 */
420 { 0x00FF, 0x00FF, 1 }, /* R74 - DC Servo 7 */
421 { 0x00FF, 0x00FF, 1 }, /* R75 - DC Servo 8 */
422 { 0x00FF, 0x00FF, 1 }, /* R76 - DC Servo 9 */
423 { 0x0FFF, 0x0000, 1 }, /* R77 - DC Servo Readback 0 */
436 { 0x00FF, 0x00FF, 0 }, /* R90 - Analogue HP 0 */
440 { 0x00FF, 0x00FF, 0 }, /* R94 - Analogue Lineout 0 */
444 { 0x0001, 0x0001, 0 }, /* R98 - Charge Pump 0 */
450 { 0x0001, 0x0001, 0 }, /* R104 - Class W 0 */
454 { 0x011F, 0x011F, 0 }, /* R108 - Write Sequencer 0 */
455 { 0x7FFF, 0x7FFF, 0 }, /* R109 - Write Sequencer 1 */
456 { 0x4FFF, 0x4FFF, 0 }, /* R110 - Write Sequencer 2 */
457 { 0x003F, 0x033F, 0 }, /* R111 - Write Sequencer 3 */
458 { 0x03F1, 0x0000, 0 }, /* R112 - Write Sequencer 4 */
462 { 0x0007, 0x0007, 0 }, /* R116 - FLL Control 1 */
463 { 0x3F77, 0x3F77, 0 }, /* R117 - FLL Control 2 */
464 { 0xFFFF, 0xFFFF, 0 }, /* R118 - FLL Control 3 */
465 { 0x7FEF, 0x7FEF, 0 }, /* R119 - FLL Control 4 */
466 { 0x001B, 0x001B, 0 }, /* R120 - FLL Control 5 */
467 { 0x003F, 0x003F, 0 }, /* R121 - GPIO Control 1 */
468 { 0x003F, 0x003F, 0 }, /* R122 - GPIO Control 2 */
469 { 0x003F, 0x003F, 0 }, /* R123 - GPIO Control 3 */
470 { 0x038F, 0x038F, 0 }, /* R124 - GPIO Control 4 */
472 { 0x00FF, 0x00FF, 0 }, /* R126 - Digital Pulls */
473 { 0x07FF, 0x03FF, 1 }, /* R127 - Interrupt Status */
474 { 0x03FF, 0x03FF, 0 }, /* R128 - Interrupt Status Mask */
475 { 0x03FF, 0x03FF, 0 }, /* R129 - Interrupt Polarity */
476 { 0x03FF, 0x03FF, 0 }, /* R130 - Interrupt Debounce */
480 { 0x0001, 0x0001, 0 }, /* R134 - EQ1 */
481 { 0x001F, 0x001F, 0 }, /* R135 - EQ2 */
482 { 0x001F, 0x001F, 0 }, /* R136 - EQ3 */
483 { 0x001F, 0x001F, 0 }, /* R137 - EQ4 */
484 { 0x001F, 0x001F, 0 }, /* R138 - EQ5 */
485 { 0x001F, 0x001F, 0 }, /* R139 - EQ6 */
486 { 0xFFFF, 0xFFFF, 0 }, /* R140 - EQ7 */
487 { 0xFFFF, 0xFFFF, 0 }, /* R141 - EQ8 */
488 { 0xFFFF, 0xFFFF, 0 }, /* R142 - EQ9 */
489 { 0xFFFF, 0xFFFF, 0 }, /* R143 - EQ10 */
490 { 0xFFFF, 0xFFFF, 0 }, /* R144 - EQ11 */
491 { 0xFFFF, 0xFFFF, 0 }, /* R145 - EQ12 */
492 { 0xFFFF, 0xFFFF, 0 }, /* R146 - EQ13 */
493 { 0xFFFF, 0xFFFF, 0 }, /* R147 - EQ14 */
494 { 0xFFFF, 0xFFFF, 0 }, /* R148 - EQ15 */
495 { 0xFFFF, 0xFFFF, 0 }, /* R149 - EQ16 */
496 { 0xFFFF, 0xFFFF, 0 }, /* R150 - EQ17 */
497 { 0xFFFF, 0xFFFF, 0 }, /* R151wm8523_dai - EQ18 */
498 { 0xFFFF, 0xFFFF, 0 }, /* R152 - EQ19 */
499 { 0xFFFF, 0xFFFF, 0 }, /* R153 - EQ20 */
500 { 0xFFFF, 0xFFFF, 0 }, /* R154 - EQ21 */
501 { 0xFFFF, 0xFFFF, 0 }, /* R155 - EQ22 */
502 { 0xFFFF, 0xFFFF, 0 }, /* R156 - EQ23 */
503 { 0xFFFF, 0xFFFF, 0 }, /* R157 - EQ24 */
507 { 0x0002, 0x0002, 0 }, /* R161 - Control Interface Test 1 */
550 { 0x0070, 0x0070, 0 }, /* R204 - Analogue Output Bias 0 */
593 { 0x0001, 0x0001, 0 }, /* R247 - FLL NCO Test 0 */
594 { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */
612 /* Gate the clock while we're updating to avoid misclocking */ in wm8904_configure_clocking()
618 switch (wm8904->sysclk_src) { in wm8904_configure_clocking()
620 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); in wm8904_configure_clocking()
623 rate = wm8904->mclk_rate; in wm8904_configure_clocking()
631 dev_dbg(codec->dev, "Using %dHz FLL clock\n", in wm8904_configure_clocking()
632 wm8904->fll_fout); in wm8904_configure_clocking()
635 rate = wm8904->fll_fout; in wm8904_configure_clocking()
639 dev_err(codec->dev, "System clock not configured\n"); in wm8904_configure_clocking()
640 return -EINVAL; in wm8904_configure_clocking()
646 wm8904->sysclk_rate = rate / 2; in wm8904_configure_clocking()
649 wm8904->sysclk_rate = rate; in wm8904_configure_clocking()
658 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); in wm8904_configure_clocking()
666 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_set_drc()
674 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); in wm8904_set_drc()
686 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_put_drc_enum()
687 int value = ucontrol->value.integer.value[0]; in wm8904_put_drc_enum()
689 if (value >= pdata->num_drc_cfgs) in wm8904_put_drc_enum()
690 return -EINVAL; in wm8904_put_drc_enum()
692 wm8904->drc_cfg = value; in wm8904_put_drc_enum()
705 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; in wm8904_get_drc_enum()
713 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_set_retune_mobile()
716 if (!pdata || !wm8904->num_retune_mobile_texts) in wm8904_set_retune_mobile()
721 cfg = wm8904->retune_mobile_cfg; in wm8904_set_retune_mobile()
724 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { in wm8904_set_retune_mobile()
725 if (strcmp(pdata->retune_mobile_cfgs[i].name, in wm8904_set_retune_mobile()
726 wm8904->retune_mobile_texts[cfg]) == 0 && in wm8904_set_retune_mobile()
727 abs(pdata->retune_mobile_cfgs[i].rate in wm8904_set_retune_mobile()
728 - wm8904->fs) < best_val) { in wm8904_set_retune_mobile()
730 best_val = abs(pdata->retune_mobile_cfgs[i].rate in wm8904_set_retune_mobile()
731 - wm8904->fs); in wm8904_set_retune_mobile()
735 dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", in wm8904_set_retune_mobile()
736 pdata->retune_mobile_cfgs[best].name, in wm8904_set_retune_mobile()
737 pdata->retune_mobile_cfgs[best].rate, in wm8904_set_retune_mobile()
738 wm8904->fs); in wm8904_set_retune_mobile()
747 pdata->retune_mobile_cfgs[best].regs[i]); in wm8904_set_retune_mobile()
757 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_put_retune_mobile_enum()
758 int value = ucontrol->value.integer.value[0]; in wm8904_put_retune_mobile_enum()
760 if (value >= pdata->num_retune_mobile_cfgs) in wm8904_put_retune_mobile_enum()
761 return -EINVAL; in wm8904_put_retune_mobile_enum()
763 wm8904->retune_mobile_cfg = value; in wm8904_put_retune_mobile_enum()
776 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; in wm8904_get_retune_mobile_enum()
791 if (wm8904->deemph) { in wm8904_set_deemph()
794 if (abs(deemph_settings[i] - wm8904->fs) < in wm8904_set_deemph()
795 abs(deemph_settings[best] - wm8904->fs)) in wm8904_set_deemph()
804 dev_dbg(codec->dev, "Set deemphasis %d\n", val); in wm8904_set_deemph()
816 ucontrol->value.enumerated.item[0] = wm8904->deemph; in wm8904_get_deemph()
825 int deemph = ucontrol->value.enumerated.item[0]; in wm8904_put_deemph()
828 return -EINVAL; in wm8904_put_deemph()
830 wm8904->deemph = deemph; in wm8904_put_deemph()
836 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
837 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
838 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
839 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
842 "Single-Ended", "Differential Line", "Differential Mic"
852 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
939 struct snd_soc_codec *codec = w->codec; in sysclk_event()
949 switch (wm8904->sysclk_src) { in sysclk_event()
977 struct snd_soc_codec *codec = w->codec; in out_pga_event()
990 reg = w->shift; in out_pga_event()
1011 return -EINVAL; in out_pga_event()
1039 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { in out_pga_event()
1040 dev_dbg(codec->dev, "Restoring DC servo state\n"); in out_pga_event()
1043 wm8904->dcs_state[dcs_l]); in out_pga_event()
1045 wm8904->dcs_state[dcs_r]); in out_pga_event()
1051 dev_dbg(codec->dev, "Calibrating DC servo\n"); in out_pga_event()
1067 } while (--timeout); in out_pga_event()
1070 dev_warn(codec->dev, "DC servo timed out\n"); in out_pga_event()
1072 dev_dbg(codec->dev, "DC servo ready\n"); in out_pga_event()
1100 wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg); in out_pga_event()
1101 wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg); in out_pga_event()
1131 SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
1137 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum);
1147 SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
1153 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum);
1163 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
1169 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
1175 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
1181 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
1200 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
1201 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
1203 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
1204 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
1215 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
1216 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
1226 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
1227 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
1264 SOC_DAPM_ENUM("HPL Mux", hpl_enum);
1270 SOC_DAPM_ENUM("HPR Mux", hpr_enum);
1276 SOC_DAPM_ENUM("LINEL Mux", linel_enum);
1282 SOC_DAPM_ENUM("LINEL Mux", liner_enum);
1292 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
1298 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
1308 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1309 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1310 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
1311 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
1320 { "Left Capture Mux", "IN1L", "IN1L" },
1321 { "Left Capture Mux", "IN2L", "IN2L" },
1322 { "Left Capture Mux", "IN3L", "IN3L" },
1324 { "Left Capture Inverting Mux", "IN1L", "IN1L" },
1325 { "Left Capture Inverting Mux", "IN2L", "IN2L" },
1326 { "Left Capture Inverting Mux", "IN3L", "IN3L" },
1328 { "Right Capture Mux", "IN1R", "IN1R" },
1329 { "Right Capture Mux", "IN2R", "IN2R" },
1330 { "Right Capture Mux", "IN3R", "IN3R" },
1332 { "Right Capture Inverting Mux", "IN1R", "IN1R" },
1333 { "Right Capture Inverting Mux", "IN2R", "IN2R" },
1334 { "Right Capture Inverting Mux", "IN3R", "IN3R" },
1336 { "Left Capture PGA", NULL, "Left Capture Mux" },
1337 { "Left Capture PGA", NULL, "Left Capture Inverting Mux" },
1339 { "Right Capture PGA", NULL, "Right Capture Mux" },
1340 { "Right Capture PGA", NULL, "Right Capture Inverting Mux" },
1397 { "HPL Mux", "DAC", "DACL" },
1398 { "HPL Mux", "Bypass", "Left Bypass" },
1400 { "HPR Mux", "DAC", "DACR" },
1401 { "HPR Mux", "Bypass", "Right Bypass" },
1403 { "LINEL Mux", "DAC", "DACL" },
1404 { "LINEL Mux", "Bypass", "Left Bypass" },
1406 { "LINER Mux", "DAC", "DACR" },
1407 { "LINER Mux", "Bypass", "Right Bypass" },
1409 { "HPL PGA", NULL, "HPL Mux" },
1410 { "HPR PGA", NULL, "HPR Mux" },
1412 { "LINEL PGA", NULL, "LINEL Mux" },
1413 { "LINER PGA", NULL, "LINER Mux" },
1427 struct snd_soc_dapm_context *dapm = &codec->dapm; in wm8904_add_widgets()
1434 switch (wm8904->devtype) { in wm8904_add_widgets()
1540 struct snd_soc_codec *codec = dai->codec; in wm8904_hw_params()
1550 wm8904->fs = params_rate(params); in wm8904_hw_params()
1551 if (wm8904->tdm_slots) { in wm8904_hw_params()
1552 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", in wm8904_hw_params()
1553 wm8904->tdm_slots, wm8904->tdm_width); in wm8904_hw_params()
1554 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, in wm8904_hw_params()
1555 wm8904->tdm_width, 2, in wm8904_hw_params()
1556 wm8904->tdm_slots); in wm8904_hw_params()
1558 wm8904->bclk = snd_soc_params_to_bclk(params); in wm8904_hw_params()
1574 return -EINVAL; in wm8904_hw_params()
1578 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk); in wm8904_hw_params()
1586 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) in wm8904_hw_params()
1587 - wm8904->fs); in wm8904_hw_params()
1589 cur_val = abs((wm8904->sysclk_rate / in wm8904_hw_params()
1590 clk_sys_rates[i].ratio) - wm8904->fs); in wm8904_hw_params()
1596 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", in wm8904_hw_params()
1603 best_val = abs(wm8904->fs - sample_rates[0].rate); in wm8904_hw_params()
1606 cur_val = abs(wm8904->fs - sample_rates[i].rate); in wm8904_hw_params()
1612 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", in wm8904_hw_params()
1618 if (wm8904->fs <= 24000) in wm8904_hw_params()
1625 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) in wm8904_hw_params()
1626 - wm8904->bclk; in wm8904_hw_params()
1634 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; in wm8904_hw_params()
1635 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", in wm8904_hw_params()
1636 bclk_divs[best].div, wm8904->bclk); in wm8904_hw_params()
1640 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); in wm8904_hw_params()
1641 aif3 |= wm8904->bclk / wm8904->fs; in wm8904_hw_params()
1667 struct snd_soc_codec *codec = dai->codec; in wm8904_set_sysclk()
1672 priv->sysclk_src = clk_id; in wm8904_set_sysclk()
1673 priv->mclk_rate = freq; in wm8904_set_sysclk()
1677 priv->sysclk_src = clk_id; in wm8904_set_sysclk()
1681 return -EINVAL; in wm8904_set_sysclk()
1684 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); in wm8904_set_sysclk()
1693 struct snd_soc_codec *codec = dai->codec; in wm8904_set_fmt()
1711 return -EINVAL; in wm8904_set_fmt()
1729 return -EINVAL; in wm8904_set_fmt()
1743 return -EINVAL; in wm8904_set_fmt()
1763 return -EINVAL; in wm8904_set_fmt()
1767 return -EINVAL; in wm8904_set_fmt()
1783 struct snd_soc_codec *codec = dai->codec; in wm8904_set_tdm_slot()
1791 /* Note that we allow configurations we can't handle ourselves - in wm8904_set_tdm_slot()
1804 return -EINVAL; in wm8904_set_tdm_slot()
1815 return -EINVAL; in wm8904_set_tdm_slot()
1819 wm8904->tdm_width = slot_width; in wm8904_set_tdm_slot()
1820 wm8904->tdm_slots = slots / 2; in wm8904_set_tdm_slot()
1864 fll_div->fll_clk_ref_div = 0; in fll_factors()
1867 fll_div->fll_clk_ref_div++; in fll_factors()
1872 return -EINVAL; in fll_factors()
1881 /* Fvco should be 90-100MHz; don't check the upper bound */ in fll_factors()
1888 return -EINVAL; in fll_factors()
1892 fll_div->fll_outdiv = div - 1; in fll_factors()
1899 fll_div->fll_fratio = fll_fratios[i].fll_fratio; in fll_factors()
1906 return -EINVAL; in fll_factors()
1912 fll_div->n = Ndiv; in fll_factors()
1916 /* Calculate fractional part - scale up so we can round. */ in fll_factors()
1927 fll_div->k = K / 10; in fll_factors()
1930 fll_div->n, fll_div->k, in fll_factors()
1931 fll_div->fll_fratio, fll_div->fll_outdiv, in fll_factors()
1932 fll_div->fll_clk_ref_div); in fll_factors()
1940 struct snd_soc_codec *codec = dai->codec; in wm8904_set_fll()
1947 if (source == wm8904->fll_src && Fref == wm8904->fll_fref && in wm8904_set_fll()
1948 Fout == wm8904->fll_fout) in wm8904_set_fll()
1954 dev_dbg(codec->dev, "FLL disabled\n"); in wm8904_set_fll()
1956 wm8904->fll_fref = 0; in wm8904_set_fll()
1957 wm8904->fll_fout = 0; in wm8904_set_fll()
1980 dev_dbg(codec->dev, "Using free running FLL\n"); in wm8904_set_fll()
1990 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); in wm8904_set_fll()
1991 return -EINVAL; in wm8904_set_fll()
2056 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); in wm8904_set_fll()
2058 wm8904->fll_fref = Fref; in wm8904_set_fll()
2059 wm8904->fll_fout = Fout; in wm8904_set_fll()
2060 wm8904->fll_src = source; in wm8904_set_fll()
2078 struct snd_soc_codec *codec = codec_dai->codec; in wm8904_digital_mute()
2093 u16 *reg_cache = codec->reg_cache; in wm8904_sync_cache()
2096 if (!codec->cache_sync) in wm8904_sync_cache()
2099 codec->cache_only = 0; in wm8904_sync_cache()
2104 for (i = 1; i < codec->driver->reg_cache_size; i++) { in wm8904_sync_cache()
2114 codec->cache_sync = 0; in wm8904_sync_cache()
2139 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { in wm8904_set_bias_level()
2140 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), in wm8904_set_bias_level()
2141 wm8904->supplies); in wm8904_set_bias_level()
2143 dev_err(codec->dev, in wm8904_set_bias_level()
2191 codec->cache_sync = 1; in wm8904_set_bias_level()
2194 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), in wm8904_set_bias_level()
2195 wm8904->supplies); in wm8904_set_bias_level()
2198 codec->dapm.bias_level = level; in wm8904_set_bias_level()
2217 .name = "wm8904-hifi",
2258 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_handle_retune_mobile_pdata()
2261 wm8904->retune_mobile_enum, in wm8904_handle_retune_mobile_pdata()
2271 wm8904->num_retune_mobile_texts = 0; in wm8904_handle_retune_mobile_pdata()
2272 wm8904->retune_mobile_texts = NULL; in wm8904_handle_retune_mobile_pdata()
2273 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { in wm8904_handle_retune_mobile_pdata()
2274 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { in wm8904_handle_retune_mobile_pdata()
2275 if (strcmp(pdata->retune_mobile_cfgs[i].name, in wm8904_handle_retune_mobile_pdata()
2276 wm8904->retune_mobile_texts[j]) == 0) in wm8904_handle_retune_mobile_pdata()
2280 if (j != wm8904->num_retune_mobile_texts) in wm8904_handle_retune_mobile_pdata()
2284 t = krealloc(wm8904->retune_mobile_texts, in wm8904_handle_retune_mobile_pdata()
2286 (wm8904->num_retune_mobile_texts + 1), in wm8904_handle_retune_mobile_pdata()
2292 t[wm8904->num_retune_mobile_texts] = in wm8904_handle_retune_mobile_pdata()
2293 pdata->retune_mobile_cfgs[i].name; in wm8904_handle_retune_mobile_pdata()
2296 wm8904->num_retune_mobile_texts++; in wm8904_handle_retune_mobile_pdata()
2297 wm8904->retune_mobile_texts = t; in wm8904_handle_retune_mobile_pdata()
2300 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", in wm8904_handle_retune_mobile_pdata()
2301 wm8904->num_retune_mobile_texts); in wm8904_handle_retune_mobile_pdata()
2303 wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts; in wm8904_handle_retune_mobile_pdata()
2304 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; in wm8904_handle_retune_mobile_pdata()
2308 dev_err(codec->dev, in wm8904_handle_retune_mobile_pdata()
2315 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_handle_pdata()
2324 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); in wm8904_handle_pdata()
2326 if (pdata->num_drc_cfgs) { in wm8904_handle_pdata()
2328 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, in wm8904_handle_pdata()
2332 wm8904->drc_texts = kmalloc(sizeof(char *) in wm8904_handle_pdata()
2333 * pdata->num_drc_cfgs, GFP_KERNEL); in wm8904_handle_pdata()
2334 if (!wm8904->drc_texts) { in wm8904_handle_pdata()
2335 dev_err(codec->dev, in wm8904_handle_pdata()
2337 pdata->num_drc_cfgs); in wm8904_handle_pdata()
2341 for (i = 0; i < pdata->num_drc_cfgs; i++) in wm8904_handle_pdata()
2342 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; in wm8904_handle_pdata()
2344 wm8904->drc_enum.max = pdata->num_drc_cfgs; in wm8904_handle_pdata()
2345 wm8904->drc_enum.texts = wm8904->drc_texts; in wm8904_handle_pdata()
2349 dev_err(codec->dev, in wm8904_handle_pdata()
2355 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", in wm8904_handle_pdata()
2356 pdata->num_retune_mobile_cfgs); in wm8904_handle_pdata()
2358 if (pdata->num_retune_mobile_cfgs) in wm8904_handle_pdata()
2369 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_probe()
2370 u16 *reg_cache = codec->reg_cache; in wm8904_probe()
2373 codec->cache_sync = 1; in wm8904_probe()
2374 codec->dapm.idle_bias_off = 1; in wm8904_probe()
2376 switch (wm8904->devtype) { in wm8904_probe()
2383 dev_err(codec->dev, "Unknown device type %d\n", in wm8904_probe()
2384 wm8904->devtype); in wm8904_probe()
2385 return -EINVAL; in wm8904_probe()
2390 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); in wm8904_probe()
2394 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) in wm8904_probe()
2395 wm8904->supplies[i].supply = wm8904_supply_names[i]; in wm8904_probe()
2397 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies), in wm8904_probe()
2398 wm8904->supplies); in wm8904_probe()
2400 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); in wm8904_probe()
2404 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), in wm8904_probe()
2405 wm8904->supplies); in wm8904_probe()
2407 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); in wm8904_probe()
2413 dev_err(codec->dev, "Failed to read ID register\n"); in wm8904_probe()
2417 dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret); in wm8904_probe()
2418 ret = -EINVAL; in wm8904_probe()
2424 dev_err(codec->dev, "Failed to read device revision: %d\n", in wm8904_probe()
2428 dev_info(codec->dev, "revision %c\n", ret + 'A'); in wm8904_probe()
2432 dev_err(codec->dev, "Failed to issue reset\n"); in wm8904_probe()
2436 /* Change some default settings - latch VU and enable ZC */ in wm8904_probe()
2461 if (wm8904->pdata) { in wm8904_probe()
2463 if (!pdata->gpio_cfg[i]) in wm8904_probe()
2467 = pdata->gpio_cfg[i] & 0xffff; in wm8904_probe()
2473 = pdata->mic_cfg[i]; in wm8904_probe()
2476 /* Set Class W by default - this will be managed by the Class in wm8904_probe()
2489 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); in wm8904_probe()
2498 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); in wm8904_probe()
2500 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); in wm8904_probe()
2509 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); in wm8904_remove()
2510 kfree(wm8904->retune_mobile_texts); in wm8904_remove()
2511 kfree(wm8904->drc_texts); in wm8904_remove()
2537 return -ENOMEM; in wm8904_i2c_probe()
2539 wm8904->devtype = id->driver_data; in wm8904_i2c_probe()
2541 wm8904->pdata = i2c->dev.platform_data; in wm8904_i2c_probe()
2543 ret = snd_soc_register_codec(&i2c->dev, in wm8904_i2c_probe()
2552 snd_soc_unregister_codec(&client->dev); in wm8904_i2c_remove()