82 	SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
84 	SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
86 	SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
89 	SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
90 	SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
97 	SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
99 	SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
100 	SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
151 	SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
152 	SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
156 	SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
157 	SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
161 	SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
165 	SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
169 	SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0),
170 	SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0),
171 	SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0),
175 	SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0),
176 	SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0),
177 	SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0),
225 	{"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
226 	{"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
231 	{"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
237 	{"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
238 	{"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
243 	{"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
249 	{"Left Input Mixer", "IN1_L P Switch", "IN1_L"},
250 	{"Left Input Mixer", "IN2_L P Switch", "IN2_L"},
251 	{"Left Input Mixer", "IN3_L P Switch", "IN3_L"},
256 	{"Right Input Mixer", "IN1_R P Switch", "IN1_R"},
257 	{"Right Input Mixer", "IN2_R P Switch", "IN2_R"},
258 	{"Right Input Mixer", "IN3_R P Switch", "IN3_R"},
357 	switch (freq) {  in aic32x4_set_dai_sysclk()
383 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {  in aic32x4_set_dai_fmt()
394 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {  in aic32x4_set_dai_fmt()
491 	switch (params_format(params)) {  in aic32x4_hw_params()
525 	switch (level) {  in aic32x4_set_bias_level()
527 		/* Switch on PLL */  in aic32x4_set_bias_level()
531 		/* Switch on NDAC Divider */  in aic32x4_set_bias_level()
535 		/* Switch on MDAC Divider */  in aic32x4_set_bias_level()
539 		/* Switch on NADC Divider */  in aic32x4_set_bias_level()
543 		/* Switch on MADC Divider */  in aic32x4_set_bias_level()
547 		/* Switch on BCLK_N Divider */  in aic32x4_set_bias_level()
554 		/* Switch off PLL */  in aic32x4_set_bias_level()
558 		/* Switch off NDAC Divider */  in aic32x4_set_bias_level()
562 		/* Switch off MDAC Divider */  in aic32x4_set_bias_level()
566 		/* Switch off NADC Divider */  in aic32x4_set_bias_level()
570 		/* Switch off MADC Divider */  in aic32x4_set_bias_level()
574 		/* Switch off BCLK_N Divider */  in aic32x4_set_bias_level()