Lines Matching full:control
49 /*Left ADC Volume Control (SSM2602_REG_LEFT_ADC_VOL)*/
50 #define LINVOL_LIN_VOL 0x01F /* Left Channel PGA Volume control …
54 /*Right ADC Volume Control (SSM2602_REG_RIGHT_ADC_VOL)*/
55 #define RINVOL_RIN_VOL 0x01F /* Right Channel PGA Volume control …
59 /*Left DAC Volume Control (SSM2602_REG_LEFT_DAC_VOL)*/
60 #define LOUT1V_LHP_VOL 0x07F /* Left Channel Headphone volume control …
64 /*Right DAC Volume Control (SSM2602_REG_RIGHT_DAC_VOL)*/
65 #define ROUT1V_RHP_VOL 0x07F /* Right Channel Headphone volume control …
69 /*Analogue Audio Path Control (SSM2602_REG_ANALOGUE_PATH)*/
70 … APANA_ENABLE_MIC_BOOST 0x001 /* Primary Microphone Amplifier gain booster control */
71 #define APANA_ENABLE_MIC_MUTE 0x002 /* Microphone Mute Control …
77 … APANA_ENABLE_MIC_BOOST2 0x100 /* Secondary Microphone Amplifier gain booster control */
79 /*Digital Audio Path Control (SSM2602_REG_DIGITAL_PATH)*/
81 #define APDIGI_DE_EMPHASIS 0x006 /* De-Emphasis Control …
82 #define APDIGI_ENABLE_DAC_MUTE 0x008 /* DAC Mute Control …
85 /*Power Down Control (SSM2602_REG_POWER)
98 #define IFACE_IFACE_FORMAT 0x003 /* Digital Audio input format control …
99 #define IFACE_AUDIO_DATA_LEN 0x00C /* Audio Data word length control …
100 #define IFACE_DAC_LR_POLARITY 0x010 /* Polarity Control for clocks in RJ,LJ and I2S mo…
101 #define IFACE_DAC_LR_SWAP 0x020 /* Swap DAC data control …
103 #define IFACE_BCLK_INVERT 0x080 /* Bit Clock Inversion control …
105 /*Sampling Control (SSM2602_REG_SAMPLING_CTRL)*/
108 #define SRATE_SAMPLE_RATE 0x03C /* Clock setting condition (Sampling rate control)…
112 /*Active Control (SSM2602_REG_ACTIVE_CTRL)*/