Lines Matching defs:comm_page

645 struct comm_page {		/*				Base	Length*/  struct
646 	u32 comm_size;		/* size of this object		0x000	4 */
647 	u32 flags;		/* See Appendix A below		0x004	4 */
648 	u32 unused;		/* Unused entry			0x008	4 */
649 	u32 sample_rate;	/* Card sample rate in Hz	0x00c	4 */
650 	u32 handshake;		/* DSP command handshake	0x010	4 */
651 	u32 cmd_start;		/* Chs. to start mask		0x014	4 */
652 	u32 cmd_stop;		/* Chs. to stop mask		0x018	4 */
653 	u32 cmd_reset;		/* Chs. to reset mask		0x01c	4 */
654 	u16 audio_format[DSP_MAXPIPES];	/* Chs. audio format	0x020	32*2 */
655 	struct sg_entry sglist_addr[DSP_MAXPIPES];
657 	u32 position[DSP_MAXPIPES];
659 	s8 vu_meter[DSP_MAXPIPES];
661 	s8 peak_meter[DSP_MAXPIPES];
663 	s8 line_out_level[DSP_MAXAUDIOOUTPUTS];
665 	s8 line_in_level[DSP_MAXAUDIOINPUTS];
667 	s8 monitors[MONITOR_ARRAY_SIZE];
669 	u32 play_coeff[MAX_PLAY_TAPS];
671 	u32 rec_coeff[MAX_REC_TAPS];
673 	u16 midi_input[MIDI_IN_BUFFER_SIZE];
675 	u8 gd_clock_state;	/* Chg Gina/Darla clock state	0xb60	1 */
676 	u8 gd_spdif_status;	/* Chg. Gina/Darla S/PDIF state	0xb61	1 */
677 	u8 gd_resampler_state;	/* Should always be 3		0xb62	1 */
678 	u8 filler2;		/*				0xb63	1 */
679 	u32 nominal_level_mask;	/* -10 level enable mask	0xb64	4 */
680 	u16 input_clock;	/* Chg. Input clock state	0xb68	2 */
681 	u16 output_clock;	/* Chg. Output clock state	0xb6a	2 */
682 	u32 status_clocks;	/* Current Input clock state	0xb6c	4 */
683 	u32 ext_box_status;	/* External box status		0xb70	4 */
684 	u32 cmd_add_buffer;	/* Pipes to add (obsolete)	0xb74	4 */
685 	u32 midi_out_free_count;
687 	u32 unused2;		/* Cyclic pipes			0xb7c	4 */
688 	u32 control_register;
690 	u32 e3g_frq_register;	/* 3G frequency register	0xb84	4 */
691 	u8 filler[24];		/* filler			0xb88	24*1 */
692 	s8 vmixer[VMIXER_ARRAY_SIZE];
694 	u8 midi_output[MIDI_OUT_BUFFER_SIZE];